Topological optimization of PLAs for yield enhancement

Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1993-10-27 DOI:10.1109/DFTVS.1993.595768

V. Chiluvuri, I. Koren

引用次数: 2

Abstract

Several topological optimization techniques have been developed to minimize the area of PLAs. Significant yield enhancement can also be achieved by minimizing the defect sensitivity of a design that is already optimized for area. The authors propose a yield enhancement technique through which the defect sensitivity of the design will be minimized without increasing the area. This reduction in critical area is achieved primarily by minimizing the wire lengths in several layers of the layout. The yield enhancement results of the proposed technique on some benchmark PLA examples are presented.

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提高成品率的聚乳酸拓扑优化

为了使pla的面积最小化，已经开发了几种拓扑优化技术。通过最小化已经针对面积进行优化的设计的缺陷敏感性，也可以实现显着的产量提高。作者提出了一种良率增强技术，通过该技术可以在不增加面积的情况下最小化设计的缺陷灵敏度。关键面积的减少主要是通过最小化布局中几层的导线长度来实现的。给出了该技术在一些PLA基准算例上的良率增强结果。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

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