Pub Date : 1993-10-27DOI: 10.1109/DFTVS.1993.595735
R. S. Collica
Yield models have been used in semiconductor manufacturing for quite some time with typically good success. Many of these yield models are used for determining the appropriate type and amount of redundancy in random access memories. The author describes the use of a yield model for SRAMs based on die level bit fail counts on a wafer through the use of a logistic regression model. The model uses a binary response for when a chip does or does not have bit failures recorded. Once a model is fit to the bit fail data, accurate yield loss estimates can be made of certain bit fail modes taking into account the amount of autocorrelation of bit fail categories on similar chips. This is necessary due to the high degree of bit fail clustering typically encountered in semiconductor manufacturing. Examples are given showing the actual versus the predicted model on a 128 kbit SRAM device. Discussion of the necessity of using a logistic model with a binary response as compared to other regression models using ordinary least squares (OLS) approaches. The benefits of this model are discussed with its assumptions and limitations. Typical applications of the model are also shown.
{"title":"A logistic regression yield model for SRAM bit fail patterns","authors":"R. S. Collica","doi":"10.1109/DFTVS.1993.595735","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595735","url":null,"abstract":"Yield models have been used in semiconductor manufacturing for quite some time with typically good success. Many of these yield models are used for determining the appropriate type and amount of redundancy in random access memories. The author describes the use of a yield model for SRAMs based on die level bit fail counts on a wafer through the use of a logistic regression model. The model uses a binary response for when a chip does or does not have bit failures recorded. Once a model is fit to the bit fail data, accurate yield loss estimates can be made of certain bit fail modes taking into account the amount of autocorrelation of bit fail categories on similar chips. This is necessary due to the high degree of bit fail clustering typically encountered in semiconductor manufacturing. Examples are given showing the actual versus the predicted model on a 128 kbit SRAM device. Discussion of the necessity of using a logistic model with a binary response as compared to other regression models using ordinary least squares (OLS) approaches. The benefits of this model are discussed with its assumptions and limitations. Typical applications of the model are also shown.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123791591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-27DOI: 10.1109/DFTVS.1993.595645
C. Aktouf, C. Robach, G. Mazaré, J. Johansson
The authors present a strategy for testing MIMD parallel machines. First they detail a functional testing methodology. Based on a functional fault model for the communications between processors, the authors propose a distributed diagnosis strategy and the test program generation process. Next, a fault-tolerant routing algorithm is proposed. Taking into account the results obtained from the testing phase, this algorithm allows successful routing of messages between fault-free cells.
{"title":"Functional testing and reconfiguration of MIMD machines","authors":"C. Aktouf, C. Robach, G. Mazaré, J. Johansson","doi":"10.1109/DFTVS.1993.595645","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595645","url":null,"abstract":"The authors present a strategy for testing MIMD parallel machines. First they detail a functional testing methodology. Based on a functional fault model for the communications between processors, the authors propose a distributed diagnosis strategy and the test program generation process. Next, a fault-tolerant routing algorithm is proposed. Taking into account the results obtained from the testing phase, this algorithm allows successful routing of messages between fault-free cells.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126871009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-27DOI: 10.1109/DFTVS.1993.595806
Graham Frearson
The authors outline a practical approach adopted to integrated current design-for-test methodologies into a VLSI chip containing several processing elements and embedded RAM. It is shown that optimizing design styles to suit the applications has resulted in the need for more than one test strategy. Global design rules concerning clocking and reset to allow scan and behavioral test are discussed. Using the T9000 virtual channel processor as an example, the integration of some of these techniques is explained.
{"title":"The T9 transputer: A practical example of the application of standard test techniques","authors":"Graham Frearson","doi":"10.1109/DFTVS.1993.595806","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595806","url":null,"abstract":"The authors outline a practical approach adopted to integrated current design-for-test methodologies into a VLSI chip containing several processing elements and embedded RAM. It is shown that optimizing design styles to suit the applications has resulted in the need for more than one test strategy. Global design rules concerning clocking and reset to allow scan and behavioral test are discussed. Using the T9000 virtual channel processor as an example, the integration of some of these techniques is explained.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116098372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-27DOI: 10.1109/DFTVS.1993.595623
L. Guerra, M. Potkonjak, J. Rabaey
Built-in-self-repair (BISR) is a hardware redundancy fault tolerance technique, where a set of spare modules is provided in addition to core operational modules. Until now, the application of BISR methodology has been limited to situations where a failed module of one type can only be replaced by a backup module of the same type. It is shown that in ASIC designs it is possible to enable replacement of modules of different types with the same spare units by exploiting the flexibility of high level synthesis solutions. Resource allocation, assignment and scheduling techniques that support a new BISR methodology are presented. All mentioned high level synthesis algorithms are developed on top of the HYPER high level synthesis system, using a novel statistical methodology for heuristic algorithm development and improvement. The effectiveness of the approach is verified and yield improvement data is presented for numerous real-life examples.
{"title":"High level synthesis techniques for efficient built-in-self-repair","authors":"L. Guerra, M. Potkonjak, J. Rabaey","doi":"10.1109/DFTVS.1993.595623","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595623","url":null,"abstract":"Built-in-self-repair (BISR) is a hardware redundancy fault tolerance technique, where a set of spare modules is provided in addition to core operational modules. Until now, the application of BISR methodology has been limited to situations where a failed module of one type can only be replaced by a backup module of the same type. It is shown that in ASIC designs it is possible to enable replacement of modules of different types with the same spare units by exploiting the flexibility of high level synthesis solutions. Resource allocation, assignment and scheduling techniques that support a new BISR methodology are presented. All mentioned high level synthesis algorithms are developed on top of the HYPER high level synthesis system, using a novel statistical methodology for heuristic algorithm development and improvement. The effectiveness of the approach is verified and yield improvement data is presented for numerous real-life examples.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129247632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-27DOI: 10.1109/DFTVS.1993.595829
N. Kumar, P. Pouliquen, A. Andreou
The performance of a memory based computational engine, a Hamming distance classifier that employs static memory cells and an analog Winner-Takes-All circuit depends on device matching in the various parts of the circuit. This dependence has been analyzed, leading to design criteria for choosing the device sizes and chip structure. The theoretical performance of a CMOS chip designed to operate in the subthreshold and transition region has been compared with the actual experimental results.
{"title":"Device mismatch limitations on performance of a Hamming distance classifier","authors":"N. Kumar, P. Pouliquen, A. Andreou","doi":"10.1109/DFTVS.1993.595829","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595829","url":null,"abstract":"The performance of a memory based computational engine, a Hamming distance classifier that employs static memory cells and an analog Winner-Takes-All circuit depends on device matching in the various parts of the circuit. This dependence has been analyzed, leading to design criteria for choosing the device sizes and chip structure. The theoretical performance of a CMOS chip designed to operate in the subthreshold and transition region has been compared with the actual experimental results.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124659733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-27DOI: 10.1109/DFTVS.1993.595826
A. Fanni, A. Giua, Enrico Sandoli
Fault diagnosis of analog circuits is a complex problem. The authors discuss how the features of neural networks of learning from examples and of generalizing may be used to solve this problem. In a detailed applicative example, it is shown how, given the voltages values in a set of test points, a network may be trained to recognize catastrophic single faults on a circuit part of a direct current motor drive. The network is then used to diagnose multiple faults on two and three components. In this case the network is generally able to detect at least one of the malfunctioning components, although less sharply than in the case of single faults.
{"title":"Neural networks for multiple fault diagnosis in analog circuits","authors":"A. Fanni, A. Giua, Enrico Sandoli","doi":"10.1109/DFTVS.1993.595826","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595826","url":null,"abstract":"Fault diagnosis of analog circuits is a complex problem. The authors discuss how the features of neural networks of learning from examples and of generalizing may be used to solve this problem. In a detailed applicative example, it is shown how, given the voltages values in a set of test points, a network may be trained to recognize catastrophic single faults on a circuit part of a direct current motor drive. The network is then used to diagnose multiple faults on two and three components. In this case the network is generally able to detect at least one of the malfunctioning components, although less sharply than in the case of single faults.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132014557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-27DOI: 10.1109/DFTVS.1993.595639
C. Low, H. Leong
The authors consider the problem of reconfiguring VLSI/WSI arrays via the degradation approach. In this approach, all elements are treated uniformly and no elements are dedicated as spares. The goal is to derive a fault-free subarray T from the defective host array such that the dimensions of T are larger than some specified minimum. This problem has been shown to be NP-complete under various switching and routing constraints. However, it is shown that a special case of the reconfiguration problem with row bypass and column rerouting capabilities, is solvable in polynomial time using network flows. Using this result, a new fast and efficient reconfiguration algorithm is proposed. Empirical study shows that the new algorithm indeed produces good results in terms of the percentages of harvest and degradation of VLSI/WSI arrays.
{"title":"On the configuration of degradable VLSI/WSI arrays","authors":"C. Low, H. Leong","doi":"10.1109/DFTVS.1993.595639","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595639","url":null,"abstract":"The authors consider the problem of reconfiguring VLSI/WSI arrays via the degradation approach. In this approach, all elements are treated uniformly and no elements are dedicated as spares. The goal is to derive a fault-free subarray T from the defective host array such that the dimensions of T are larger than some specified minimum. This problem has been shown to be NP-complete under various switching and routing constraints. However, it is shown that a special case of the reconfiguration problem with row bypass and column rerouting capabilities, is solvable in polynomial time using network flows. Using this result, a new fast and efficient reconfiguration algorithm is proposed. Empirical study shows that the new algorithm indeed produces good results in terms of the percentages of harvest and degradation of VLSI/WSI arrays.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129709570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-27DOI: 10.1109/DFTVS.1993.595628
H. Kari, Heikki Saikkonen, F. Lombardi
The authors present new improved methods for detecting latent sector faults in a disk subsystem as caused by media deterioration of the disk magnetic storage material. Usually, sectors in a disk are accessed using uneven patterns causing some of the sectors to be accessed only seldom. In case of media deterioration on the rarely accessed sectors, a latent disk fault may remain undetected for a long time. To detect latent sector faults, a disk is scanned through periodically. An adaptive algorithm is proposed to utilize the idle time for the disk for scanning commonly used disks that comply with SCSI-II interface standards.
{"title":"Detection of defective media in disks","authors":"H. Kari, Heikki Saikkonen, F. Lombardi","doi":"10.1109/DFTVS.1993.595628","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595628","url":null,"abstract":"The authors present new improved methods for detecting latent sector faults in a disk subsystem as caused by media deterioration of the disk magnetic storage material. Usually, sectors in a disk are accessed using uneven patterns causing some of the sectors to be accessed only seldom. In case of media deterioration on the rarely accessed sectors, a latent disk fault may remain undetected for a long time. To detect latent sector faults, a disk is scanned through periodically. An adaptive algorithm is proposed to utilize the idle time for the disk for scanning commonly used disks that comply with SCSI-II interface standards.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128473972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-27DOI: 10.1109/DFTVS.1993.595814
E. Sogomonyan, M. Gössel
It is shown that an arbitrary n-tupel of M-ary Boolean functions can be systematically implemented as a self-testing combinational circuit. This is achieved by the use of a parity bit and of one or more replicates of a selected part of the monitored circuit. The party bit and the functional bits are thus jointly designed rather than in separation. The circuit is then called a self-parity circuit. In comparison to a separate implementation of a parity prediction function, the hardware costs can be significantly reduced. The circuit can be used in test mode and in normal operation mode for online fault detection. In normal online operation, faults may be detected with some degree of latency.
{"title":"Design of self-parity combinational circuits for self-testing and on-line detection","authors":"E. Sogomonyan, M. Gössel","doi":"10.1109/DFTVS.1993.595814","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595814","url":null,"abstract":"It is shown that an arbitrary n-tupel of M-ary Boolean functions can be systematically implemented as a self-testing combinational circuit. This is achieved by the use of a parity bit and of one or more replicates of a selected part of the monitored circuit. The party bit and the functional bits are thus jointly designed rather than in separation. The circuit is then called a self-parity circuit. In comparison to a separate implementation of a parity prediction function, the hardware costs can be significantly reduced. The circuit can be used in test mode and in normal operation mode for online fault detection. In normal online operation, faults may be detected with some degree of latency.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126552924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-27DOI: 10.1109/DFTVS.1993.595768
V. Chiluvuri, I. Koren
Several topological optimization techniques have been developed to minimize the area of PLAs. Significant yield enhancement can also be achieved by minimizing the defect sensitivity of a design that is already optimized for area. The authors propose a yield enhancement technique through which the defect sensitivity of the design will be minimized without increasing the area. This reduction in critical area is achieved primarily by minimizing the wire lengths in several layers of the layout. The yield enhancement results of the proposed technique on some benchmark PLA examples are presented.
{"title":"Topological optimization of PLAs for yield enhancement","authors":"V. Chiluvuri, I. Koren","doi":"10.1109/DFTVS.1993.595768","DOIUrl":"https://doi.org/10.1109/DFTVS.1993.595768","url":null,"abstract":"Several topological optimization techniques have been developed to minimize the area of PLAs. Significant yield enhancement can also be achieved by minimizing the defect sensitivity of a design that is already optimized for area. The authors propose a yield enhancement technique through which the defect sensitivity of the design will be minimized without increasing the area. This reduction in critical area is achieved primarily by minimizing the wire lengths in several layers of the layout. The yield enhancement results of the proposed technique on some benchmark PLA examples are presented.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121083637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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