{"title":"Current sensor and test processor design for integration of logic and IDDQ testing of CMOS ICs","authors":"Md. Altaf-Ul-Amin, Z. M. Darus","doi":"10.1109/SMELEC.1998.781172","DOIUrl":null,"url":null,"abstract":"This paper presents an approach to integrate logic and IDDQ testing which are crucial in verifying the functionality and improving the reliability of CMOS ICs. Work presented in this paper involves the design of an off-chip current sensor and a compatible test processor for the aforementioned purpose. The sensor is an analog circuit and the test processor is a digital ASIC. The performance of both the sensor and the test processor has been verified through computer simulation. Fault simulation results show that reasonable numbers of test vectors generated by the scheme used in this work are able to detect all detectable stuck-at faults in some ISCAS'85 benchmark circuits.","PeriodicalId":356206,"journal":{"name":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMELEC.1998.781172","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper presents an approach to integrate logic and IDDQ testing which are crucial in verifying the functionality and improving the reliability of CMOS ICs. Work presented in this paper involves the design of an off-chip current sensor and a compatible test processor for the aforementioned purpose. The sensor is an analog circuit and the test processor is a digital ASIC. The performance of both the sensor and the test processor has been verified through computer simulation. Fault simulation results show that reasonable numbers of test vectors generated by the scheme used in this work are able to detect all detectable stuck-at faults in some ISCAS'85 benchmark circuits.
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