Pub Date : 1998-11-24DOI: 10.1109/SMELEC.1998.781141
Y. Hua, E. Liu, L. An, D.K.W. Chau
Some lots of wafers were reported with low yield due to ANADC pattern functional failure. SEM, EDX and 155 Wright etch techniques were used to identify the root causes. Cross sectional results found the nodules on substrate at the contact area. EDX analysis confirmed them to be silicon nodules. After 155 Wright etch [100] square silicon crystalline hillocks were found on the substrate at the contact area. It is concluded that silicon nodules on the substrate at the contact area had resulted in an open circuit and low yield. These silicon nodules were due to Si precipitation on the substrate of the contacts.
{"title":"The Si precipitation problem in aluminium alloy (Al-Si-Cu) metallization","authors":"Y. Hua, E. Liu, L. An, D.K.W. Chau","doi":"10.1109/SMELEC.1998.781141","DOIUrl":"https://doi.org/10.1109/SMELEC.1998.781141","url":null,"abstract":"Some lots of wafers were reported with low yield due to ANADC pattern functional failure. SEM, EDX and 155 Wright etch techniques were used to identify the root causes. Cross sectional results found the nodules on substrate at the contact area. EDX analysis confirmed them to be silicon nodules. After 155 Wright etch [100] square silicon crystalline hillocks were found on the substrate at the contact area. It is concluded that silicon nodules on the substrate at the contact area had resulted in an open circuit and low yield. These silicon nodules were due to Si precipitation on the substrate of the contacts.","PeriodicalId":356206,"journal":{"name":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","volume":"921 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120942242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-24DOI: 10.1109/SMELEC.1998.781138
S. Marsh, A. Long, G. Edwards, B. J. Buck, N.A. Peniket, M. Geen, S. Wadsworth
The market for information technology and wireless communication systems is growing rapidly to meet the increasing demand for greater capacity on existing networks and new systems with greater bandwidth. Access points to these networks are moving closer to individual desks and homes, driving up the volumes, and driving down the prices, of the required components. GaAs MMIC technology is ideally placed to meet these requirements, bringing with it small size and weight, low cost and inherent reproducibility. The MESFET, HEMT and HBT MMIC processes at GMMT have produced ASICs for commercial products in such systems, and are available as foundry services for external customers to design their own ASIC chips.
{"title":"GaAs MMIC technology for IT and wireless communications","authors":"S. Marsh, A. Long, G. Edwards, B. J. Buck, N.A. Peniket, M. Geen, S. Wadsworth","doi":"10.1109/SMELEC.1998.781138","DOIUrl":"https://doi.org/10.1109/SMELEC.1998.781138","url":null,"abstract":"The market for information technology and wireless communication systems is growing rapidly to meet the increasing demand for greater capacity on existing networks and new systems with greater bandwidth. Access points to these networks are moving closer to individual desks and homes, driving up the volumes, and driving down the prices, of the required components. GaAs MMIC technology is ideally placed to meet these requirements, bringing with it small size and weight, low cost and inherent reproducibility. The MESFET, HEMT and HBT MMIC processes at GMMT have produced ASICs for commercial products in such systems, and are available as foundry services for external customers to design their own ASIC chips.","PeriodicalId":356206,"journal":{"name":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125117171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-24DOI: 10.1109/SMELEC.1998.781151
Yit-Wooi Lim, T. Yeoh
CMOS SRAM cell cold failure analysis is not easily performed under a room temperature environment. However, by using the signature analysis method, the transistor failure cell can be identified by directly measuring the transistor parameters from the isolated SRAM cell. The cell isolation technique for signature analysis is sensitive enough to capture the abnormal electrical signature of the SRAM cell cold failure. The technique was used on the analysis of SRAM cell cold failure from a 2-layer metal fab process. The SRAM cell and its transistors were physically and electrically isolated without any problem. The failure signature of the SRAM cell cold failure which failed stuck at "1" at a single bit address during testing, was successfully analyzed. N+ drain junction leakage and threshold voltage degradation was identified as the root cause of the cold failure.
{"title":"Novel cell isolation technique for the analysis of CMOS SRAM cell cold failure","authors":"Yit-Wooi Lim, T. Yeoh","doi":"10.1109/SMELEC.1998.781151","DOIUrl":"https://doi.org/10.1109/SMELEC.1998.781151","url":null,"abstract":"CMOS SRAM cell cold failure analysis is not easily performed under a room temperature environment. However, by using the signature analysis method, the transistor failure cell can be identified by directly measuring the transistor parameters from the isolated SRAM cell. The cell isolation technique for signature analysis is sensitive enough to capture the abnormal electrical signature of the SRAM cell cold failure. The technique was used on the analysis of SRAM cell cold failure from a 2-layer metal fab process. The SRAM cell and its transistors were physically and electrically isolated without any problem. The failure signature of the SRAM cell cold failure which failed stuck at \"1\" at a single bit address during testing, was successfully analyzed. N+ drain junction leakage and threshold voltage degradation was identified as the root cause of the cold failure.","PeriodicalId":356206,"journal":{"name":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129900553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-24DOI: 10.1109/SMELEC.1998.781155
A.U. Lagies, L. Gohler, J. Sigg, P. Turkes, R. Kraus
A mathematical description for the degradation of semiconductor devices and electrical circuits is presented. It is based on the assumption that the reason for degradation is destruction of the internal structures, caused by the input of energy. The formulation is tested with the simulation of an IGBT module. Additionally, a method is presented to shorten the simulation time as much as possible.
{"title":"Degradation modeling of semiconductor devices and electrical circuits","authors":"A.U. Lagies, L. Gohler, J. Sigg, P. Turkes, R. Kraus","doi":"10.1109/SMELEC.1998.781155","DOIUrl":"https://doi.org/10.1109/SMELEC.1998.781155","url":null,"abstract":"A mathematical description for the degradation of semiconductor devices and electrical circuits is presented. It is based on the assumption that the reason for degradation is destruction of the internal structures, caused by the input of energy. The formulation is tested with the simulation of an IGBT module. Additionally, a method is presented to shorten the simulation time as much as possible.","PeriodicalId":356206,"journal":{"name":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123310159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-24DOI: 10.1109/SMELEC.1998.781144
K. Lim, X. Zhou
A simple analytical threshold voltage equation for modelling nonuniform MOSFET channel doping is derived, which takes the peak doping concentration and peak location as inputs with a single process-dependent fitting parameter. The model has been verified with extensive numerical simulation results and can be applied to real devices for a wide range of nonuniform doping profiles with a simple, empirical parameter extraction.
{"title":"Modelling of threshold voltage with non-uniform substrate doping [MOSFET]","authors":"K. Lim, X. Zhou","doi":"10.1109/SMELEC.1998.781144","DOIUrl":"https://doi.org/10.1109/SMELEC.1998.781144","url":null,"abstract":"A simple analytical threshold voltage equation for modelling nonuniform MOSFET channel doping is derived, which takes the peak doping concentration and peak location as inputs with a single process-dependent fitting parameter. The model has been verified with extensive numerical simulation results and can be applied to real devices for a wide range of nonuniform doping profiles with a simple, empirical parameter extraction.","PeriodicalId":356206,"journal":{"name":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127142839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-24DOI: 10.1109/SMELEC.1998.781139
Y. Hua, S.L. Lim, L. An, Z.R. Guo, Y.K. Fan
Silicon crystalline defects in production silicon wafers affect the yield. In this paper, the 155 Wright etch was used to identify the root causes of silicon crystalline defects. A few low yield cases are studied and the different types of crystalline defects and their possible root causes and preventative measures taken are discussed.
{"title":"Studies on stacking faults and crystalline defects in fabrication silicon wafer substrate","authors":"Y. Hua, S.L. Lim, L. An, Z.R. Guo, Y.K. Fan","doi":"10.1109/SMELEC.1998.781139","DOIUrl":"https://doi.org/10.1109/SMELEC.1998.781139","url":null,"abstract":"Silicon crystalline defects in production silicon wafers affect the yield. In this paper, the 155 Wright etch was used to identify the root causes of silicon crystalline defects. A few low yield cases are studied and the different types of crystalline defects and their possible root causes and preventative measures taken are discussed.","PeriodicalId":356206,"journal":{"name":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130067745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-24DOI: 10.1109/SMELEC.1998.781166
M. Mahdi, S. Selvakennedy, P. Poopalan, H. Ahmad
Saturation parameters including gain, input signal power and output power were studied for erbium doped fibre amplifiers (EDFA). Knowledge of these parameters will enable a better design of EDFAs for operation as a power amplifier. In this saturated regime, gain saturation is defined as the gain at 3 dB gain compression from the unsaturated gain for a specific fibre length and pump power. Therefore, the output saturation power, P/sub osat/, and input saturation signal power, P/sub isat/, are defined as the output power and input signal power at which gain saturation occurs. The effects of pump power and fibre length were also studied in this paper.
{"title":"Saturation parameters of erbium doped fibre amplifiers","authors":"M. Mahdi, S. Selvakennedy, P. Poopalan, H. Ahmad","doi":"10.1109/SMELEC.1998.781166","DOIUrl":"https://doi.org/10.1109/SMELEC.1998.781166","url":null,"abstract":"Saturation parameters including gain, input signal power and output power were studied for erbium doped fibre amplifiers (EDFA). Knowledge of these parameters will enable a better design of EDFAs for operation as a power amplifier. In this saturated regime, gain saturation is defined as the gain at 3 dB gain compression from the unsaturated gain for a specific fibre length and pump power. Therefore, the output saturation power, P/sub osat/, and input saturation signal power, P/sub isat/, are defined as the output power and input signal power at which gain saturation occurs. The effects of pump power and fibre length were also studied in this paper.","PeriodicalId":356206,"journal":{"name":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115161392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-24DOI: 10.1109/SMELEC.1998.781169
T. H. Ting, M. Ahmad, Roy Kooh Jinn Chye, R. Wagiran, B. Suparjo
An intensive study has been conducted for the development of the MIMOS 0.8 /spl mu/m CMOS technology. Issues such as device design and characterization have been given much consideration. NMOS and PMOS transistors have been designed from basic concepts and using simulation tools such as TSUPREM-4 and MEDICI. Device design constraints such as threshold voltage variation, off-state leakage current and drain-induced barrier lowering (DIBL) effects have been seriously examined to improve device performance. Furthermore, performance criteria such as drive current capability have also been examined. Extraction of device characteristics from silicon has been performed on a test chip. Based on experimental results, numerous I-V plots are presented and the data are discussed in terms of output and transfer characteristics and surface DIBL leakage current.
{"title":"Device design, fabrication and characterization of 0.8 /spl mu/m CMOS technology","authors":"T. H. Ting, M. Ahmad, Roy Kooh Jinn Chye, R. Wagiran, B. Suparjo","doi":"10.1109/SMELEC.1998.781169","DOIUrl":"https://doi.org/10.1109/SMELEC.1998.781169","url":null,"abstract":"An intensive study has been conducted for the development of the MIMOS 0.8 /spl mu/m CMOS technology. Issues such as device design and characterization have been given much consideration. NMOS and PMOS transistors have been designed from basic concepts and using simulation tools such as TSUPREM-4 and MEDICI. Device design constraints such as threshold voltage variation, off-state leakage current and drain-induced barrier lowering (DIBL) effects have been seriously examined to improve device performance. Furthermore, performance criteria such as drive current capability have also been examined. Extraction of device characteristics from silicon has been performed on a test chip. Based on experimental results, numerous I-V plots are presented and the data are discussed in terms of output and transfer characteristics and surface DIBL leakage current.","PeriodicalId":356206,"journal":{"name":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134517627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-24DOI: 10.1109/SMELEC.1998.781189
S. Shaari, K. Kandiah
The beam propagation method (BPM) was used to study a 4/spl times/4 active switch with electro-optical effects in a titanium diffused lithium niobate (LiNbO/sub 3/:Ti) based directional coupler, and the results were used to develop the design. This design is capable of de-multiplexing wavelengths from two groups, 1100 nm to 1300 nm and 1500 nm to 1600 nm.
{"title":"Wavelength demultiplexing study on LiNbO/sub 3/ directional coupler elements using beam propagation method","authors":"S. Shaari, K. Kandiah","doi":"10.1109/SMELEC.1998.781189","DOIUrl":"https://doi.org/10.1109/SMELEC.1998.781189","url":null,"abstract":"The beam propagation method (BPM) was used to study a 4/spl times/4 active switch with electro-optical effects in a titanium diffused lithium niobate (LiNbO/sub 3/:Ti) based directional coupler, and the results were used to develop the design. This design is capable of de-multiplexing wavelengths from two groups, 1100 nm to 1300 nm and 1500 nm to 1600 nm.","PeriodicalId":356206,"journal":{"name":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133779509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-24DOI: 10.1109/SMELEC.1998.781188
Q. Khosru, M. Uddin, M.R. Khan
A simple and effective analytical model is developed to calculate the lifetime of an electron trapped in the oxide layer of a metal-oxide-semiconductor (MOS) device using quantum analysis. A new approach applying transmission line techniques is introduced to study the time evolution of the electron wave function localized in a trap quantum well in the MOS device oxide. Treating it as a one dimensional problem, with tunneling probabilities through both oxide/metal and oxide/semiconductor interfaces, and exploiting the effective similarity with the time evolution of an electron wave packet localized in a double barrier quantum well, a model is developed to calculate the lifetime of a trapped electron under flat band conditions. It is further extended to calculate the effective lifetime of electrons trapped at various trap centers in the oxide layer under externally applied electric fields. Results thus obtained show reasonable agreement and consistency with physical concepts and experimental observations.
{"title":"A simple approach to study time evolution of trapped electrons in metal-oxide-semiconductor devices","authors":"Q. Khosru, M. Uddin, M.R. Khan","doi":"10.1109/SMELEC.1998.781188","DOIUrl":"https://doi.org/10.1109/SMELEC.1998.781188","url":null,"abstract":"A simple and effective analytical model is developed to calculate the lifetime of an electron trapped in the oxide layer of a metal-oxide-semiconductor (MOS) device using quantum analysis. A new approach applying transmission line techniques is introduced to study the time evolution of the electron wave function localized in a trap quantum well in the MOS device oxide. Treating it as a one dimensional problem, with tunneling probabilities through both oxide/metal and oxide/semiconductor interfaces, and exploiting the effective similarity with the time evolution of an electron wave packet localized in a double barrier quantum well, a model is developed to calculate the lifetime of a trapped electron under flat band conditions. It is further extended to calculate the effective lifetime of electrons trapped at various trap centers in the oxide layer under externally applied electric fields. Results thus obtained show reasonable agreement and consistency with physical concepts and experimental observations.","PeriodicalId":356206,"journal":{"name":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125704436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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