Prospects for high-aspect-ratio FinFETs in low-power logic

Abstract

As we reduce transistor capacitances, node capacitances are limited by wiring, setting a minimum power dissipation determined by the number of gates, the mean wire length, the mean switching rate, and the supply voltage VDD. With thermally-activated, FETs, the off-state leakage Ioff and target on-current Ion then determine the minimum feasible VDD, and the IC clock frequency can then be increased only at the expense of increased power consumption. Tunnel transistors [1] offer subthreshold characteristics steeper than 60mV/decade, but achieving high Ion at low Ioff and low VDD is challenging. Subthreshold logic [2] operates at lowVDD, but is slow because of low Ion. Here we propose low-power logic using high-aspect-ratio finFETs, devices we have fabricated with few-nm body thicknesses and 180nm height [3]. If these can fabricated at ~20nm pitch, then the fin surface area can exceed its footprint area - i.e. the area the transistor occupies on the IC - by ~10:1. IC performance can be then improved by maintaining fixed VDD, but with reduced FET footprint area hence reduced die size and therefore reduced wiring capacitance, or can be improved by reducing VDD to ~300mV while maintaining large Ion per unit IC die area.