Key issues in the design of a fault-tolerant core avionics computer based on the mesh architecture

Abstract

Greater integration of avionics and flight control electronics with the need for higher reliability while maintaining or improving safety and availability and the need for reduced line maintenance costs are key drivers for the examination of a fault tolerant core computer architecture. The authors' approach is to develop a computer using commercially available microprocessors and memory with an ASIC performing the fault management. They use a tightly synchronous mesh architecture with distributed dynamic fault detection, isolation and reconfiguration. They examine key impediments to the achievements of fault tolerance for the mesh architecture.<>