Software-based self-test generation for microprocessors with high-level decision diagrams

Abstract

Software-based self-testing (SBST) is a well known non-intrusive method for processor testing. Its applications have been intensively studied by the research community for the last decades. Generally, the inextinguishable attention to this method is mainly caused by continuous growth of complexity of modern processors that poses new research challenges. One of these challenges is automated generation of software-based self-tests. Through the years the main research trend was focused on reducing the processor representation complexity by shifting the modeling process towards more general abstraction layers. This paper presents the approach for high-level processor modeling, which is the next convolution of SBST methodology. We propose the methodology for processor modeling at behavioral level that can be used for automatic generation of SBST programs. The method leads to significant complexity reduction compared to RT-level and as experimental results show the efficiency of SBST in terms of fault coverage is not compromised in comparison to state-of-the-art SBST approaches.