SIMOX SOI surface smoothing for gate oxide integrity and reliability

L. Allen, D. Fenner, W. Skinner, R. Chandonnet, S.E. Deziel, R. Torti, N. Toyoda
{"title":"SIMOX SOI surface smoothing for gate oxide integrity and reliability","authors":"L. Allen, D. Fenner, W. Skinner, R. Chandonnet, S.E. Deziel, R. Torti, N. Toyoda","doi":"10.1109/SOI.1999.819880","DOIUrl":null,"url":null,"abstract":"A significant reliability aspect regarding commercial application of SOI is the consistency of the device gate oxide integrity (GOI). This research focuses on the smoothing of SIMOX SOI surfaces for advanced CMOS applications with improved GOI and reliability. As shown in an atomic force microscope (AFM) image, as-received samples of full dose single-implant SIMOX annealed in an Ar ambient show a distinct [100] tiling with a measured peak-to-valley surface roughness ranging from /spl sim/55 /spl Aring/ to /spl sim/70 /spl Aring/. These [100] faceted surface features result from silicon surface bond reconstruction during the 1310/spl deg/C SIMOX anneal temperature into their lowest free energy configuration. For the specific samples examined, the facets were typically 0.5 /spl mu/m in diameter with a mean deviation R(a) of 7.1 /spl Aring/ and R(rms) at 8.9 /spl Aring/. In order to reduce the faceting features as well as the surface roughness, a gas cluster ion beam (GCIB) method of surface smoothing was applied to the full dose single implant SIMOX samples.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOI.1999.819880","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

Abstract

A significant reliability aspect regarding commercial application of SOI is the consistency of the device gate oxide integrity (GOI). This research focuses on the smoothing of SIMOX SOI surfaces for advanced CMOS applications with improved GOI and reliability. As shown in an atomic force microscope (AFM) image, as-received samples of full dose single-implant SIMOX annealed in an Ar ambient show a distinct [100] tiling with a measured peak-to-valley surface roughness ranging from /spl sim/55 /spl Aring/ to /spl sim/70 /spl Aring/. These [100] faceted surface features result from silicon surface bond reconstruction during the 1310/spl deg/C SIMOX anneal temperature into their lowest free energy configuration. For the specific samples examined, the facets were typically 0.5 /spl mu/m in diameter with a mean deviation R(a) of 7.1 /spl Aring/ and R(rms) at 8.9 /spl Aring/. In order to reduce the faceting features as well as the surface roughness, a gas cluster ion beam (GCIB) method of surface smoothing was applied to the full dose single implant SIMOX samples.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
SIMOX SOI表面平滑栅极氧化物的完整性和可靠性
关于SOI的商业应用,一个重要的可靠性方面是器件栅极氧化物完整性(GOI)的一致性。本研究的重点是SIMOX SOI表面的平滑,用于先进的CMOS应用,提高GOI和可靠性。如原子力显微镜(AFM)图像所示,在氩气环境中退火的全剂量单植入SIMOX样品显示出明显的[100]平铺,测量到的峰谷表面粗糙度范围为/spl sim/55 /spl sim/70 /spl Aring/。这些[100]面形特征是在1310/spl℃的SIMOX退火温度下硅表面键重建到其最低自由能构型的结果。对于所检测的特定样品,切面直径通常为0.5 /spl mu/m,平均偏差R(a)为7.1 /spl Aring/, R(rms)为8.9 /spl Aring/。为了降低SIMOX样品的表面粗糙度,采用气簇离子束(GCIB)方法对SIMOX样品进行表面平滑处理。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
A novel 0.7 V two-port 6T SRAM memory cell structure with single-bit-line simultaneous read-and-write access (SBLSRWA) capability using partially-depleted SOI CMOS dynamic-threshold technique Power amplifiers on thin-film-silicon-on-insulator (TFSOI) technology Single chip wireless systems using SOI Buried oxide fringing capacitance: a new physical model and its implication on SOI device scaling and architecture A bandgap circuit operating up to 300/spl deg/C using lateral bipolar transistors in thin-film CMOS-SOI technology
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1