Architecture and performance of 3-dimensional SOI circuits

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI:10.1109/SOI.1999.819850

R. Zhang, K. Roy, D. Janes

引用次数: 28

Abstract

In this paper, potential three-dimensional SOI CMOS VLSI circuit structures are laid out. Chip area, layout complexities, process costs, and impact on circuit performance are compared and discussed.

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三维SOI电路的结构与性能

本文给出了潜在的SOI CMOS VLSI三维电路结构。对芯片面积、布局复杂性、工艺成本以及对电路性能的影响进行了比较和讨论。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)

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