{"title":"Deep-submicron design challenges for a dual-core 64b UltraSPARC microprocessor implementation","authors":"T. Takayanagi, J. L. Shin, J. Su, A. Leon","doi":"10.1109/ICICDT.2004.1309933","DOIUrl":null,"url":null,"abstract":"A processor core, originally designed in a 0.5/spl mu/m Al process, is redesigned for a 0.13/spl mu/m Cu process to create a dual-core processor with 1MB integrated L2 cache, offering an efficient performance to power ratio for compute-dense server applications. Circuit design challenges, including negative bias temperature instability (NBTI), leakage, coupling noise and intra die process variation are discussed.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"19 5","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICDT.2004.1309933","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A processor core, originally designed in a 0.5/spl mu/m Al process, is redesigned for a 0.13/spl mu/m Cu process to create a dual-core processor with 1MB integrated L2 cache, offering an efficient performance to power ratio for compute-dense server applications. Circuit design challenges, including negative bias temperature instability (NBTI), leakage, coupling noise and intra die process variation are discussed.
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