Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309983
V. Chang, C. Chen, Y. Jin, C. Chen, T. Lee, S. Chen, M. Liang
A semi-empirical model was developed to calculate the equivalent oxide thickness (EOT) and leakage current of nitrided gate oxide by hypothetically dividing the nitrided oxide into a nitride/oxide (N/O) stack. The calculations agree well with the experimental data (R/sup 2/ > 0.99) for various nitrided oxides with EOT ranging from 12 to 23 /spl Aring/. A model-based strategy for the optimization of nitrided oxide is presented and demonstrated by a nitrided oxide sample which meets both the EOT and leakage current requirements of ITRS 65-nm low standby power (LSTP) technology and shows no electron mobility degradation. The model forecasts that a nitrogen concentration of 20% approximately the maximum from Oxide nitridation processes - satisfies the ITRS requirements for production until Year 2007. The production afterwards will require alternative dielectrics such as N/O stack or high-k materials for greater leakage current reductions.
{"title":"Optimization and scaling limit forecast of nitrided gate oxide using an equivalent nitride/oxide (N/O) stack model","authors":"V. Chang, C. Chen, Y. Jin, C. Chen, T. Lee, S. Chen, M. Liang","doi":"10.1109/ICICDT.2004.1309983","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309983","url":null,"abstract":"A semi-empirical model was developed to calculate the equivalent oxide thickness (EOT) and leakage current of nitrided gate oxide by hypothetically dividing the nitrided oxide into a nitride/oxide (N/O) stack. The calculations agree well with the experimental data (R/sup 2/ > 0.99) for various nitrided oxides with EOT ranging from 12 to 23 /spl Aring/. A model-based strategy for the optimization of nitrided oxide is presented and demonstrated by a nitrided oxide sample which meets both the EOT and leakage current requirements of ITRS 65-nm low standby power (LSTP) technology and shows no electron mobility degradation. The model forecasts that a nitrogen concentration of 20% approximately the maximum from Oxide nitridation processes - satisfies the ITRS requirements for production until Year 2007. The production afterwards will require alternative dielectrics such as N/O stack or high-k materials for greater leakage current reductions.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116666940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309906
G. Koh, Y. Hwang, Sun-Ghil Lee, Suyoun Lee, K. Ryoo, Joon-Min Park, Yun-Heub Song, Soomin Ahn, Changwook Jeong, F. Yeung, Y. Kim, J.-B. Park, G. Jeong, H. Jeong, Keunnam Kim
PRAM(Phase-Change RAM) is a promising memory that can solve the problems of conventional memory and has the nearly ideal memory characteristics. We reviewed the issues for high density PRAM integration. Writing current reduction is the most urgent problem for high density PRAM realization. We presented process factors which affect the writing current and the result of improvement. Finally we demonstrated results of 64Mb PRAM integration based on 0.18/spl mu/m CMOS technology.
{"title":"PRAM process technology","authors":"G. Koh, Y. Hwang, Sun-Ghil Lee, Suyoun Lee, K. Ryoo, Joon-Min Park, Yun-Heub Song, Soomin Ahn, Changwook Jeong, F. Yeung, Y. Kim, J.-B. Park, G. Jeong, H. Jeong, Keunnam Kim","doi":"10.1109/ICICDT.2004.1309906","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309906","url":null,"abstract":"PRAM(Phase-Change RAM) is a promising memory that can solve the problems of conventional memory and has the nearly ideal memory characteristics. We reviewed the issues for high density PRAM integration. Writing current reduction is the most urgent problem for high density PRAM realization. We presented process factors which affect the writing current and the result of improvement. Finally we demonstrated results of 64Mb PRAM integration based on 0.18/spl mu/m CMOS technology.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125117185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309950
F. Pellizzer, A. Spandre, S. Alba, A. Pirovano
Phase change memories based on chalcogenide materials are being studied as an alternative for nonvolatile information storage, because they can become attractive for technology nodes beyond 65 nm due to their intrinsic scalability In this paper we propose a first analysis of plasma damage of phase memory cells, starting from the basic electrical characteristics of storage elements and then including the effects of different selecting devices. Taking into account the architecture of phase change arrays, we will evaluate typical etching conditions and try to understand any possible impact on cell parameters and performances. Finally we will show some electrical results on real devices, integrated in a standard CMOS process in 0.18 /spl mu/m technology.
{"title":"Analysis of plasma damage on phase change memory cells","authors":"F. Pellizzer, A. Spandre, S. Alba, A. Pirovano","doi":"10.1109/ICICDT.2004.1309950","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309950","url":null,"abstract":"Phase change memories based on chalcogenide materials are being studied as an alternative for nonvolatile information storage, because they can become attractive for technology nodes beyond 65 nm due to their intrinsic scalability In this paper we propose a first analysis of plasma damage of phase memory cells, starting from the basic electrical characteristics of storage elements and then including the effects of different selecting devices. Taking into account the architecture of phase change arrays, we will evaluate typical etching conditions and try to understand any possible impact on cell parameters and performances. Finally we will show some electrical results on real devices, integrated in a standard CMOS process in 0.18 /spl mu/m technology.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125371438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309939
T. Karnik, Vivek De, S. Borkar, T. Karnik
Future high performance microprocessor design with technology scaling beyond 90nm will face a major challenge - parameter variations. Design practice will have to change from deterministic design to statistical design for variation tolerance. This paper discusses process, voltage and temperature variations, and their impact on circuits and microarchitecture. Possible solutions to reduce the impact of parameter variations on digital and analog circuits, and to achieve higher target frequencies are also presented.
{"title":"Statistical design for variation tolerance: key to continued Moore's law","authors":"T. Karnik, Vivek De, S. Borkar, T. Karnik","doi":"10.1109/ICICDT.2004.1309939","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309939","url":null,"abstract":"Future high performance microprocessor design with technology scaling beyond 90nm will face a major challenge - parameter variations. Design practice will have to change from deterministic design to statistical design for variation tolerance. This paper discusses process, voltage and temperature variations, and their impact on circuits and microarchitecture. Possible solutions to reduce the impact of parameter variations on digital and analog circuits, and to achieve higher target frequencies are also presented.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122869671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309977
G. Upadhyaya, J.L. Shohet, J.L. Lauer
Radiation induced damage during the plasma processing of semiconductor materials adversely affects device reliability. Our group has shown in the past that Vacuum Ultraviolet (VUV) radiation (10nm-200nm) can beneficially deplete the charge deposited on the surface of the semiconductor by temporarily increasing the conductivity of the dielectric. The increase in conductivity has mainly been attributed to the generation of photoemission current and formation of electron hole pairs in the dielectric. In this paper, we discuss the steps involved in developing a model for VUV-semiconductor dielectric interactions based on the well-known Monte Carlo method. The statistical information obtained from this simulation will be compared to the experimental values obtained by exposing silicon nitride wafers to synchrotron radiation of energy 20eV. The simulation predicts the surface potential on the wafer due to photoemission. Experimentally measured surface potentials on the dielectric are used to check the validity of the simulation. Of the different process that can occur when a photon is incident on an atom, we concentrate mainly on photoemission of an electron. Consequently, the elastic and inelastic scattering events experienced by the electron during the course of its motion inside the dielectric are also considered. A modified form of the screened Rutherford formula, which approximates the Mott cross-section, as developed by Browning et. al., has been applied in this simulation. Initial simulation results will be presented.
{"title":"Monte-Carlo simulation of the effects of vacuum ultraviolet radiation on electronic materials","authors":"G. Upadhyaya, J.L. Shohet, J.L. Lauer","doi":"10.1109/ICICDT.2004.1309977","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309977","url":null,"abstract":"Radiation induced damage during the plasma processing of semiconductor materials adversely affects device reliability. Our group has shown in the past that Vacuum Ultraviolet (VUV) radiation (10nm-200nm) can beneficially deplete the charge deposited on the surface of the semiconductor by temporarily increasing the conductivity of the dielectric. The increase in conductivity has mainly been attributed to the generation of photoemission current and formation of electron hole pairs in the dielectric. In this paper, we discuss the steps involved in developing a model for VUV-semiconductor dielectric interactions based on the well-known Monte Carlo method. The statistical information obtained from this simulation will be compared to the experimental values obtained by exposing silicon nitride wafers to synchrotron radiation of energy 20eV. The simulation predicts the surface potential on the wafer due to photoemission. Experimentally measured surface potentials on the dielectric are used to check the validity of the simulation. Of the different process that can occur when a photon is incident on an atom, we concentrate mainly on photoemission of an electron. Consequently, the elastic and inelastic scattering events experienced by the electron during the course of its motion inside the dielectric are also considered. A modified form of the screened Rutherford formula, which approximates the Mott cross-section, as developed by Browning et. al., has been applied in this simulation. Initial simulation results will be presented.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123864685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309904
Sung-young Lee, Keunwoo Kim
New types of memories with potentially ideal properties are topic of growing interest. Among the candidates, Ferroelectric RAM, Phase change RAM, and Magnetic RAM appear to be most promising for commercialization. In this paper, these memories will be reviewed in respect of current technology status, technical challenges encountered and solutions for technological barriers.
{"title":"Prospects of emerging new memory technologies","authors":"Sung-young Lee, Keunwoo Kim","doi":"10.1109/ICICDT.2004.1309904","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309904","url":null,"abstract":"New types of memories with potentially ideal properties are topic of growing interest. Among the candidates, Ferroelectric RAM, Phase change RAM, and Magnetic RAM appear to be most promising for commercialization. In this paper, these memories will be reviewed in respect of current technology status, technical challenges encountered and solutions for technological barriers.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124453201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309934
A. Khan
Chip designers transitioning from VLSI to System-on-Chip (SoC) design are experiencing a major increase in design complexity: Project scale, design content and the technical requirements for successful design are all going up concurrently and, in many cases, exponentially. At the same time, business success increasingly requires first-to-market delivery of innovative and competitive new products with rapid ramp to volume production. In many cases, the manufacturing life of individual designs is trending downwards, from many years to (typically) about one year. Conventional design approaches - which evolved over time to address VLSI design requirements - often do not scaleup to address requirements in this era of nanometer SoCs. At a practical level, this may result in multiple silicon iterations to address all of the product requirements correctly, which is likely to jeopardize business success in the present stringent business climate: There is simply not enough time to iterate-to-success and still achieve business goals. These two forces increasing design complexity and reduced manufacturing windows - place a great (and growing) emphasis on achieving first silicon success with high-yielding designs; this is increasingly the key difference between business success and failure for SoC design. The presentation focuses on sharing recent design experience in developing several, industry-first system-on-chip (SoC) ICs, as these relate to improvements in design methods (including design best practices to verify design performance across the manufacturing range), new design technologies, design methodology, and circuit and chip electrical / physical design techniques which contributed to first silicon success. The results enabled successful achievement of business and technical objectives set for the designs. The material may be useful for design engineers and general / technical management interested in the design and development of nanometer system-on-chip ICs.
{"title":"Recent developments in high-performance system-on-chip IC design","authors":"A. Khan","doi":"10.1109/ICICDT.2004.1309934","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309934","url":null,"abstract":"Chip designers transitioning from VLSI to System-on-Chip (SoC) design are experiencing a major increase in design complexity: Project scale, design content and the technical requirements for successful design are all going up concurrently and, in many cases, exponentially. At the same time, business success increasingly requires first-to-market delivery of innovative and competitive new products with rapid ramp to volume production. In many cases, the manufacturing life of individual designs is trending downwards, from many years to (typically) about one year. Conventional design approaches - which evolved over time to address VLSI design requirements - often do not scaleup to address requirements in this era of nanometer SoCs. At a practical level, this may result in multiple silicon iterations to address all of the product requirements correctly, which is likely to jeopardize business success in the present stringent business climate: There is simply not enough time to iterate-to-success and still achieve business goals. These two forces increasing design complexity and reduced manufacturing windows - place a great (and growing) emphasis on achieving first silicon success with high-yielding designs; this is increasingly the key difference between business success and failure for SoC design. The presentation focuses on sharing recent design experience in developing several, industry-first system-on-chip (SoC) ICs, as these relate to improvements in design methods (including design best practices to verify design performance across the manufacturing range), new design technologies, design methodology, and circuit and chip electrical / physical design techniques which contributed to first silicon success. The results enabled successful achievement of business and technical objectives set for the designs. The material may be useful for design engineers and general / technical management interested in the design and development of nanometer system-on-chip ICs.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133492088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309940
Chitra K. Subramanian, T. Andre, J. Nahas, B. Garni, H. Lin, A. Omair, W. Martino
A 4 Mbit "Toggle" MRAM, built in 0.18 micron five level metal CMOS technology, using a 1.55 /spl mu/m/sup 2/ bitcell with a single toggling magneto tunnel junction is described. The "Toggle" memory uses unidirectional programming currents controlled by switched local mirror circuits to achieve robust write operation. The isolated read architecture supports a 25 ns asynchronous cycle time operation, driven by balanced three input current mirror sense amplifiers.
{"title":"Design aspects of a 4 Mbit 0.18 /spl mu/m 1T1MTJ toggle MRAM memory","authors":"Chitra K. Subramanian, T. Andre, J. Nahas, B. Garni, H. Lin, A. Omair, W. Martino","doi":"10.1109/ICICDT.2004.1309940","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309940","url":null,"abstract":"A 4 Mbit \"Toggle\" MRAM, built in 0.18 micron five level metal CMOS technology, using a 1.55 /spl mu/m/sup 2/ bitcell with a single toggling magneto tunnel junction is described. The \"Toggle\" memory uses unidirectional programming currents controlled by switched local mirror circuits to achieve robust write operation. The isolated read architecture supports a 25 ns asynchronous cycle time operation, driven by balanced three input current mirror sense amplifiers.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"315 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133666968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309976
Janet L Barth, Kenneth A Ieee, eee Christian Label, Poivey
The space radiation environment can lead to extremely harsh operating conditions for spacecraft electronic systems. A hardness assurance methodology must be followed to assure that the space radiation environment does not compromise the functionality and performance of space-based systems during the mission lifetime. The methodology, outlined in this paper, includes a definition of the radiation environment, assessment of the radiation sensitivity of parts, worst-case analysis of the impact of radiation effects, and part acceptance decisions which are likely to include mitigation measures.
{"title":"Radiation assurance for the space environment","authors":"Janet L Barth, Kenneth A Ieee, eee Christian Label, Poivey","doi":"10.1109/ICICDT.2004.1309976","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309976","url":null,"abstract":"The space radiation environment can lead to extremely harsh operating conditions for spacecraft electronic systems. A hardness assurance methodology must be followed to assure that the space radiation environment does not compromise the functionality and performance of space-based systems during the mission lifetime. The methodology, outlined in this paper, includes a definition of the radiation environment, assessment of the radiation sensitivity of parts, worst-case analysis of the impact of radiation effects, and part acceptance decisions which are likely to include mitigation measures.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128868182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-10-04DOI: 10.1109/ICICDT.2004.1309921
N. Engelhardt, G. Schindler, W. Steinhogl, G. Steinlesberger, M. Traving
The investigation of interconnects with CDs of future technology nodes is limited to direct writing techniques for pattern definition, as next generation lithography is still under investigation. To by-pass the throughput limitations of direct writing, allowing the fabrication of only a limited number of test structures for process adaptations and electrical characterization, alternative approaches were developed. Standard stepper manufacturing lithography was used in combination with additional process tricks to fabricate a large number of test structures across the wafers with CDs down to 20nm, however, at the expense of a relaxed pitch. For a study of the scaling limits of copper damascene and subtractive aluminium metallization, a removable spacer technique and a hard mask trim were developed, respectively. Thus damascene trenches and RIE-masks with deep sub-100nm CDs could be prepared. The electrical characterization of Cu nano interconnects shows that the ITRS requirement for the conductor resistivity will not be met, not even with cooling, in future technology generations. The ITRS red brick wall for barrier films, however, is getting cracks. Barrier functionality with film thicknesses below end-of-roadmap thickness requirements was demonstrated with excellent barrier integrity regarding line-to-line leakage after anneals and after excessive BTS tests. First results on electromigration behaviour of Cu nano interconnects are also encouraging. Results on Al are underway.
{"title":"Investigation of nano interconnects for an early experimental assessment of future interconnect challenges","authors":"N. Engelhardt, G. Schindler, W. Steinhogl, G. Steinlesberger, M. Traving","doi":"10.1109/ICICDT.2004.1309921","DOIUrl":"https://doi.org/10.1109/ICICDT.2004.1309921","url":null,"abstract":"The investigation of interconnects with CDs of future technology nodes is limited to direct writing techniques for pattern definition, as next generation lithography is still under investigation. To by-pass the throughput limitations of direct writing, allowing the fabrication of only a limited number of test structures for process adaptations and electrical characterization, alternative approaches were developed. Standard stepper manufacturing lithography was used in combination with additional process tricks to fabricate a large number of test structures across the wafers with CDs down to 20nm, however, at the expense of a relaxed pitch. For a study of the scaling limits of copper damascene and subtractive aluminium metallization, a removable spacer technique and a hard mask trim were developed, respectively. Thus damascene trenches and RIE-masks with deep sub-100nm CDs could be prepared. The electrical characterization of Cu nano interconnects shows that the ITRS requirement for the conductor resistivity will not be met, not even with cooling, in future technology generations. The ITRS red brick wall for barrier films, however, is getting cracks. Barrier functionality with film thicknesses below end-of-roadmap thickness requirements was demonstrated with excellent barrier integrity regarding line-to-line leakage after anneals and after excessive BTS tests. First results on electromigration behaviour of Cu nano interconnects are also encouraging. Results on Al are underway.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124436337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：