High performance 0.1 um pMOSFETs with optimized poly-Si and poly-SiGe gates

E. Josse, T. Skotnicki, M. Jurczak, F. Martin, M. Paoli, B. Tormen, C. Hernandez, I. Campidelli
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Abstract

In this paper, we demonstrate that a careful optimization of poly-Si and polySiGe gates is able to extend these materials validity, thus postponing the need for metal gate. Improving dopant drive-in and interfacial distribution with fine-grain columnar poly-Si or increasing interfacial activation with poly-SiGe drastically reduces gate poly depletion and helps in suppressing B penetration. Using these options, we show highly performant 0.12 and 0.10 μm pMOS at 1.5V and 1.2V, with drive current as high as 350 μA/μm for IOFF=1 nA/μm and 300μA/μm for IOFF=25 nA/μm, respectively.
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高性能0.1 um pmosfet与优化的多晶硅和多晶硅栅极
在本文中,我们证明了对多晶硅和多晶硅栅极的仔细优化能够延长这些材料的有效性,从而推迟对金属栅极的需求。用细晶柱状多晶硅改善掺杂剂的注入和界面分布,或用多晶硅增加界面活化,可显著减少栅极多晶硅耗竭,有助于抑制B渗透。利用这些选项,我们在1.5V和1.2V下获得了高性能的0.12和0.10 μm pMOS,当IOFF=1 nA/μm时驱动电流高达350 μA/μm,当IOFF=25 nA/μm时驱动电流高达300μA/μm。
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