30th European Solid-State Device Research Conference最新文献

英文中文

The influence of silicon interstitial clusters on the Reverse Short Channel Effect 硅隙团簇对反向短通道效应的影响

30th European Solid-State Device Research Conference

Pub Date : 2001-10-01 DOI: 10.1109/ESSDERC.2000.194742

C. Tsamis, D. Tsoukalas, A. Tserepi, E. Tsoi

引用次数: 0

High performance 0.1 um pMOSFETs with optimized poly-Si and poly-SiGe gates 高性能0.1 um pmosfet与优化的多晶硅和多晶硅栅极

30th European Solid-State Device Research Conference

Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194836

E. Josse, T. Skotnicki, M. Jurczak, F. Martin, M. Paoli, B. Tormen, C. Hernandez, I. Campidelli

In this paper, we demonstrate that a careful optimization of poly-Si and polySiGe gates is able to extend these materials validity, thus postponing the need for metal gate. Improving dopant drive-in and interfacial distribution with fine-grain columnar poly-Si or increasing interfacial activation with poly-SiGe drastically reduces gate poly depletion and helps in suppressing B penetration. Using these options, we show highly performant 0.12 and 0.10 μm pMOS at 1.5V and 1.2V, with drive current as high as 350 μA/μm for IOFF=1 nA/μm and 300μA/μm for IOFF=25 nA/μm, respectively.

在本文中，我们证明了对多晶硅和多晶硅栅极的仔细优化能够延长这些材料的有效性，从而推迟对金属栅极的需求。用细晶柱状多晶硅改善掺杂剂的注入和界面分布，或用多晶硅增加界面活化，可显著减少栅极多晶硅耗竭，有助于抑制B渗透。利用这些选项，我们在1.5V和1.2V下获得了高性能的0.12和0.10 μm pMOS，当IOFF=1 nA/μm时驱动电流高达350 μA/μm，当IOFF=25 nA/μm时驱动电流高达300μA/μm。

引用次数: 0

PLEDs for Integration with MOS Circuits 用于与MOS电路集成的led

30th European Solid-State Device Research Conference

Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194848

L. Heinrich, J. Horstmann, K. Goser

A new promising way for the monolithic integration of light emitting devices on the top of MOS circuits is discribed. The active layer consists of PPV or MeLPPP light emitting polymer material (LEP) with an ITO cathode and a metallic anode. All process steps, including the possibility of dry etching of the active layer and structuration of the upper electrode, are typical for MOS-technology. Currentvoltage and current-intensity measurements of the devices are done for characterisation. These polymeric light emitting diodes (PLED) allow the monolithic integration of MOS microelectronic circuits and light emitting devices on a silicon chip forming one

提出了在MOS电路上单片集成发光器件的新途径。活性层由具有ITO阴极和金属阳极的PPV或MeLPPP发光聚合物材料(LEP)组成。所有的工艺步骤，包括干法蚀刻有源层的可能性和上电极的结构，都是典型的mos技术。器件的电流电压和电流强度测量是为了进行表征。这些聚合物发光二极管(PLED)允许MOS微电子电路和发光器件在硅片上形成一个单片集成

引用次数: 0

High Voltage MOS Transistor with a Folded n- Region for Flash Technology 用于闪存技术的n区折叠高压MOS晶体管

30th European Solid-State Device Research Conference

Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194757

F. Hofmann, W. Rosner, E. Landgraf

Floating gate devices like EEPROM and Flash memory require high voltages up to 20 V for programming and erase operations. This high voltage can only be handled with large MOS transistors. A common approach is to form a drift region which increases the on-resistance of the transistor. Here an extra voltage drop between the contact and the transistor channel is gernerated. In order to save chip area, a transistor is presented with the high resistive drift regions folded into the trenches on both sides of the gate.

像EEPROM和闪存这样的浮门器件需要高达20 V的高电压来进行编程和擦除操作。这种高电压只能用大型MOS晶体管来处理。一种常见的方法是形成一个增加晶体管导通电阻的漂移区。在触点和晶体管通道之间产生额外的电压降。为了节省芯片面积，晶体管的高阻漂移区被折叠到栅极两侧的沟槽中。

引用次数: 1

Scalable High Voltage Trenchgate Transistor for Flash 用于闪存的可扩展高压沟栅晶体管

30th European Solid-State Device Research Conference

Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194794

E. Landgraf, F. Hofmann, H. von Philipsborn

A trench-gate n-MOSFET suitable for high voltage operation as required for flash memories or LCD-Displays is studied. The transistor channel is folded into the substrate along the walls of a trench. This geometry offers area scalability while keeping minimum dimensions of channel length and ldd drift region needed to deal with the high voltages. The maximum drain voltage of 15V for the transistors examined is limited by breakdown of the reverse biased drainsubstrate junction. Short channel effects as DIBL or punchthrough are suppressed due to the concave corner effect for structures down to 0.6 m gate footprint.

研究了一种适用于快闪存储器或lcd显示器高电压工作的沟槽栅n-MOSFET。晶体管通道沿着沟槽壁折叠到基板中。这种几何结构提供了区域可扩展性，同时保持了处理高电压所需的通道长度和ldd漂移区域的最小尺寸。所测晶体管的最大漏极电压为15V，受反向偏置漏极衬底结击穿的限制。短通道效应，如DIBL或穿孔，由于凹角效应的结构小于0.6 m栅极足迹被抑制。

引用次数: 0

Transient I-V-Characteristics of OLEDs with Deep Traps 深阱oled的瞬态i - v特性

30th European Solid-State Device Research Conference

Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194810

S. Scheinert, G. Paasch, P. Nguyen, S. Berleb, W. Brutting

Measured current-voltage-characteristics of OLEDs show a large hysteresis for different sweep directions. To clarified this peculiarity we have carried out 2D simulations of transient current-voltage characteristics with a systematic variation of the relevant parameters to investigate this characteristics. It turns out that the transient behaviour can be explained by deep traps. Due to the high energy gap of organic materials deep traps can lie far from the bands. Further, the thermal velocity of the carriers is extremely low and consequently the time constant for trap recharging is very high. Therefore, a high delay time is necessary to measure the reverse steady-state current and to prevent the hysteresis effects.

实测的oled电流电压特性在不同的扫描方向上有较大的滞后。为了澄清这一特性，我们对瞬态电流-电压特性进行了二维模拟，并系统地改变了相关参数来研究这一特性。事实证明，瞬态行为可以用深阱来解释。由于有机物质的高能隙，深圈闭可以位于远离能带的地方。此外，载流子的热速度极低，因此陷阱再充电的时间常数非常高。因此，测量反向稳态电流和防止迟滞效应需要较高的延迟时间。

引用次数: 4

Technology and System Integration of CMOS Image Sensors CMOS图像传感器技术与系统集成

30th European Solid-State Device Research Conference

Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194724

J. Holz, I. Koren, U. Ramacher

The major drawback of the CMOS image sensors when compared to CCD devices is reduced image quality at low illumination due to lower quantum efficiency and larger leakage current of the CMOS photodiodes. In this paper, a novel photodiode structure is presented. Only minor changes to the original CMOS process were applied that don't affect the parameters of other devices. The quantum efficiency of the novel photodiode was nearly doubled and the leakage current was decreased by almost 2 orders of magnitude with respect to a source/drain junction photodiode. The concept is expected to be also applicable to future CMOS processes. This makes the benefits of the system integration of sensor and signal processing on a single CMOS chip available to applications requiring good image quality at low-light levels.

与CCD器件相比，CMOS图像传感器的主要缺点是由于CMOS光电二极管的量子效率较低和泄漏电流较大，在低照度下图像质量下降。本文提出了一种新型的光电二极管结构。仅对原始CMOS工艺进行了微小的更改，不影响其他器件的参数。与源漏结型光电二极管相比，该新型光电二极管的量子效率提高了近一倍，漏电流降低了近2个数量级。该概念预计也适用于未来的CMOS工艺。这使得在单个CMOS芯片上集成传感器和信号处理的系统优势可用于需要在低光照水平下获得良好图像质量的应用。

引用次数: 0

Atomistic Insights into Ultra-Shallow Junction Formation 原子论对超浅结形成的见解

30th European Solid-State Device Research Conference

Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194718

P. Griffin

引用次数: 0

High-Voltage Drain Extended MOS Transistors for 0.18 um Logic CMOS Process 用于0.18 um逻辑CMOS工艺的高压漏极扩展MOS晶体管

30th European Solid-State Device Research Conference

Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194793

J. Mitros, C. Tsai, Hisashi Shichijo, Keith Edmund Kunz, A. Morton, D. Goodpaster, D. Mosher, T. Efland

Complementary high-voltage drain extended (DE) MOS transistors were implemented into Texas Instruments' state-of-the-art production advanced analog and digital 1.5-1.8 V CMOS technology (1), (2). These transistors allow for 5-V drain operating voltage using the core gate oxide and have drain breakdown voltages V. Experimental results along with Suprem4 and MEDICI simulation results are presented to explain their operation. The novel p-channel transistors use an isolated compensated p-well as a drain extension. The n-channel version uses n-well as a drain extension. Experimental test results of , , and plots demonstrate DE-MOS performance. The work was focused on performance optimization with zero process modification and hence no cost adder.

互补的高压漏极扩展(DE) MOS晶体管被应用到德州仪器最先进的生产先进的模拟和数字1.5-1.8 V CMOS技术中(1)，(2)。这些晶体管允许使用核心栅极氧化物的5 V漏极工作电压，并具有漏极击穿电压V。新型p沟道晶体管采用隔离补偿p阱作为漏极扩展。n通道版本使用n井作为漏极扩展。实验测试结果和图显示了DE-MOS的性能。这项工作的重点是在零流程修改的情况下进行性能优化，因此没有成本增加。

引用次数: 29

Recent Progress on Advanced Interconnects 先进互联技术的最新进展

30th European Solid-State Device Research Conference

Pub Date : 2000-09-11 DOI: 10.1109/ESSDERC.2000.194720

M. Moussavi

This paper gives an overview of the international state of the art to overcome critical issues of advanced interconnects. Introduction Prior to the most challenging solutions on optical interconnects, IC makers have to find viable processes and materials for short and mid term requirements. For the resistivity requirement of 2.2 μΩ.cm (sum of barrier and metal resistivities) copper has been chosen to be integrated in a damascene architecture. The interlevel metal insulator effective dielectric constant requirement in the range of 1.5 to 2 can be achieved by using porous silica. The following sections will describe, step by step, critical issues in the integration of these materials with reference to the recent publications. Interconnect schemes analysis In this section, we present RC analysis only with material change. The dimensions (metal width and space) for each generation correspond to the minimum requirements of the ITRS. Effective (barrier and metal) resistivity of 3.5 μΩ.cm for Al and 2.2 μΩ.cm for Cu have been chosen. Finally, the metal height remains constant from one design rule to another. This model gives simulation results presented in figure 1. These results show clearly that from 0.25 μm to 0.1 μm, substitution of Al by Cu and SiO2 by k=3 and k=2 dielectric materials keeps quasi constant the RC, while unchanged combination of metal and dielectric, drastically increases the parasitics in the following generation. For Cu based interconnects, dual Damascene architecture is adopted using different strategies which are classified in two categories (self aligned and not self aligned structures). Figures 2-5 show 2 examples of fabrication steps and their related SEM views: i) Via first at via level as a self aligned structure ii) Via first at trench level as a not self aligned one. In both examples, absence of shift between lines and vias lead to a well defined structure. In case of misalignments, the self aligned strategy allows reduced via size and as designed meat space while the second strategy gives a reduced metal space and as designed via size. Technological issues Ebeam lithography has been used for extremely narrow geometries with available negative photo resists. Recent significant progress on 193 nm lithography demonstrates the possibility of DUV techniques for 0.12 μm generation as illustrated in figure 6. To verify the results predicted by the simulation model, one has to fabricate a multilevel interconnect structure with new materials. Different steps with potential issues are listed below: • Low k dielectric ⇒ Effective dielectric constant, adhesion, moisture absorption, mechanical and thermal stability, chemical compatibility with different reactants, heat dissipation Concerning isolation, the material impact on total capacitance and thermal conductivity is summarized in figure 7. The total capacitance has been measured with inter metal line low k and inter layer SiO2. Xerogel dielectrics (k=2.4) allow close to 50% reduct

本文概述了克服先进互连的关键问题的国际技术状况。在最具挑战性的光互连解决方案之前，IC制造商必须找到可行的工艺和材料，以满足短期和中期需求。对于电阻率要求为2.2 μΩ。Cm(屏障和金属电阻率的总和)铜被选择集成在大马士革的建筑中。采用多孔二氧化硅可达到层间金属绝缘子有效介电常数在1.5 ~ 2范围内的要求。以下各节将逐步说明将这些材料与最近的出版物结合起来的关键问题。互连方案分析在本节中，我们只介绍材料变化的RC分析。每一代的尺寸(金属宽度和空间)符合ITRS的最低要求。有效(屏障和金属)电阻率为3.5 μΩ。cm为Al和2.2 μΩ。用cm表示Cu。最后，金属高度从一个设计规则到另一个设计规则保持不变。该模型给出的仿真结果如图1所示。结果表明，从0.25 μm到0.1 μm, k=3和k=2介质材料替代Al和SiO2使RC保持准常数，而金属和介质的组合不变，使RC急剧增加。对于基于Cu的互连，采用双大马士革架构，使用不同的策略，分为两类(自排列和非自排列结构)。图2-5显示了制造步骤的2个示例及其相关的SEM视图:i)首先在孔水平上通孔作为自对准结构ii)首先在沟槽水平上通孔作为非自对准结构。在这两个例子中，没有线和过孔之间的移位导致了一个定义良好的结构。在不对齐的情况下，自对齐策略允许减少通过尺寸和设计的肉空间，而第二种策略提供减少的金属空间和设计的通过尺寸。技术问题Ebeam光刻已用于极窄的几何形状与可用的负光刻胶。最近193 nm光刻技术的重大进展证明了0.12 μm DUV技术的可能性，如图6所示。为了验证仿真模型预测的结果，必须使用新材料制作多层互连结构。•低介电常数⇒有效介电常数、粘附性、吸湿性、机械和热稳定性、与不同反应物的化学相容性、散热性。关于隔离，材料对总电容和导热系数的影响总结在图7中。用金属间线低k和层间SiO2测量了总电容。干凝胶电介质(k=2.4)可以减少近50%的电容，但它的导热系数比SiO2小10倍，这可能会导致可靠性问题。•电介质蚀刻和剥离(光刻后)⇒槽型和通孔型，剥离剂与低k材料的相容性，铜清洗(通过)正如贝尔实验室所描述的那样，低k材料的蚀刻相当具有挑战性(1)。具有高偏压功率的氟碳化学物质通常用于破坏强Si-O键，而在纯有机电介质的情况下，例如丝绸材料，活性蚀刻剂是氧。常规稀HF法对侧壁铜污染的净化效果较好。然而，光盘损耗是无法避免的。此外，由于先进的低k材料的相对孔隙率，必须开发新的清洁化学物质，以在硬掩膜水平上进行抗蚀剥离(2)。•扩散势垒沉积⇒共形性、势垒电阻率和性能与厚度的关系、对Cu和下方电介质的粘附性。适合更具侵略性特征的新势垒研究集中在CVD WxN(3)或TaN(4)和化学沉积Co(P)或Ni(P)(5)上。然而，这些材料在0.18 μm以下几何形状上的集成能力必须得到证明。例如，化学Co(P)材料的阻挡性能数据的最小厚度为50 nm。如图8所示，有效电阻率为2.2 μΩ。Cm可以通过急剧减小200μΩ的厚度来获得。Cm屏障(0.1 μm金属宽度降至7 nm)或选择8 nm厚的30 μΩ。厘米的障碍。对于线路水平，厚度的影响比电阻率值的影响重要得多。•Cu沉积⇒镀层的一致性(新技术的填充能力)、附着力和纯度由于CVD前驱体或在电镀化学中大量使用添加剂而提高。在超共形或自下而上填充铜的情况下，可以解决填充小特征的问题(6)。根据Sematech的报道(7)，由于膜的机械强度较差，抛光干凝胶damascene结构是困难的，并且需要在线面上和蚀刻后沉积共形氧化物衬里和封盖层。在本节中，我们给出一些集成示例，包括在不同金属/介质组合下RC减少方面的比较电气结果。我们在第一节中提出的模拟模型已经通过实验验证，在0.18 μm双级金属互连中，Cu/Silk和Cu/SiO2之间的RC减少了40%(8)。IBM最近(9)第三次比较了不同金属/介电组合之间的金属电容。对于最小间距为0.63 μm且线路电阻恒定的情况，Cu/FSG与Al/FSG或Cu/HSG相比，总RC延迟减少了10%(图9)。使用Flare材料(k=2.8)，与TEOS电介质相比，0.24/0.24 μm线/空间的布线电容减少了30%以上(松下(10))。多孔二氧化硅可获得较低的介电常数值。Sematech已经报道了Cu/xerogel集成(7)(图10-11)。最后，在气隙结构下可以得到k=1的最终值。图13显示了我们小组报道的基于SiOC/气隙结构的2级金属化的SEM横截面(11)。将该互连方案与Cu/SiO2的互连方案进行了比较，结果表明，在0.32μm的金属空间内，SiOCAirGap介质的互连总电容提高了55%。结论从文献中几个多层互连的结果可以看出，先进互连的新材料引入带来的许多困难挑战是可以解决的。进一步的改进涉及低k材料的蚀刻轮廓，以及有利于无空隙，低电阻金属线和过孔的屏障厚度减少。即使优化了工艺步骤，在不放松螺距的情况下，RC也只能在一种材料从一代改变到另一代时保持不变。这对研发和未来的生产都是一个严重的限制，因为技术鉴定需要大量的物理、电气和可靠性表征。

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30th European Solid-State Device Research Conference

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