An efficient yield enhancement from inline defect control and in-situ advanced process control

Abstract

Defects coming from backend metal process always impact device yield seriously, and it is hard to be repaired in the DRAM manufacturing. A good inline monitor mechanism is a key factor to have a fast and stable yield improvement. Most of defect monitors take measurements on some major process layers, due to the limit capacity of inspection tool and cost issue. Sampling monitor has a potential risk to miss some killer defect and cause yield drop. How to effectively find the killer and use an inline monitor mechanism to stop the impact tool or process is very important. This work addresses how to use the defect sampling inspection to control well the metal layer baseline defect and combine with the inline advanced process control (APC) mechanism to in-situ control the killer defects on the non-sampled wafer or non-monitored layer.