Pub Date : 2004-12-01DOI: 10.1109/SMTW.2004.1393711
Min-Hsiung Hung, Rui-Wen Ho, F. Cheng
In This work, new-generation software technologies and object-oriented technologies, such as Web services, XML signature, XML encryption, UML, etc., are used to develop an e-Diagnostics framework for semiconductor factories. The proposed framework can achieve the automaton of diagnostic processes and the integration of diagnostics information under a secure communication infrastructure. Specifically, several measures, such as single sign-on authentication and authorization, confirmation of data accuracy, assurance of information confidentiality, management of system users, and auditing of system operations, are designed to enhance the overall system security. The proposed framework can be applied to construct e-Diagnostics systems for the semiconductor industry.
{"title":"An e-Diagnostics framework with security considerations for semiconductor factories","authors":"Min-Hsiung Hung, Rui-Wen Ho, F. Cheng","doi":"10.1109/SMTW.2004.1393711","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393711","url":null,"abstract":"In This work, new-generation software technologies and object-oriented technologies, such as Web services, XML signature, XML encryption, UML, etc., are used to develop an e-Diagnostics framework for semiconductor factories. The proposed framework can achieve the automaton of diagnostic processes and the integration of diagnostics information under a secure communication infrastructure. Specifically, several measures, such as single sign-on authentication and authorization, confirmation of data accuracy, assurance of information confidentiality, management of system users, and auditing of system operations, are designed to enhance the overall system security. The proposed framework can be applied to construct e-Diagnostics systems for the semiconductor industry.","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127661100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393723
T. Luoh, Changrui Liao, Li-Chung Yang, Ling-Wu Yang, Chi-Tung Huang, H. Shih, Kuang-Chao Chen, H. Chung, J. Ku, Chih-Yuan Lu
Plasma damaged 0.18 /spl mu/m flash memory device has been resolved by integrating advanced process control with fault detection and classification (APC FDC) system in ILD HDP PSG process. PSG plasma damage to device was detected by real-time monitoring APC control system with multivariate statistically calculation to detect out-of-control conditions within five minutes. The unhealthy recipe contents and the hardware healthy status are detected by integrating APC FDC system. After we analyzing the fault detection and classification function, APC system successfully predicts the same results as wafer acceptance test and wafer sort yield. Recipe and hardware are modified to eliminate the plasma damage according the analysis results.
{"title":"Process optimization by advanced process control with fault detection system for flash memory","authors":"T. Luoh, Changrui Liao, Li-Chung Yang, Ling-Wu Yang, Chi-Tung Huang, H. Shih, Kuang-Chao Chen, H. Chung, J. Ku, Chih-Yuan Lu","doi":"10.1109/SMTW.2004.1393723","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393723","url":null,"abstract":"Plasma damaged 0.18 /spl mu/m flash memory device has been resolved by integrating advanced process control with fault detection and classification (APC FDC) system in ILD HDP PSG process. PSG plasma damage to device was detected by real-time monitoring APC control system with multivariate statistically calculation to detect out-of-control conditions within five minutes. The unhealthy recipe contents and the hardware healthy status are detected by integrating APC FDC system. After we analyzing the fault detection and classification function, APC system successfully predicts the same results as wafer acceptance test and wafer sort yield. Recipe and hardware are modified to eliminate the plasma damage according the analysis results.","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133055669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393704
Yih-Yi Lee, N. Fan
How to build up a system to translate the quantity & delivery demand of customer to the manufacturing control in foundry fab which provides complex delivery service is the key for customer orientation - supply chain driven. Advanced target delivery system (ATDS) is the mechanism to translate the quantity & delivery demand of customer to the manufacturing control for pushing lots with accurate delivery according to MPSI of PC for foundry fabs. Function for monitoring the delivery status and perforate auto-change lot priority is a great contribution for foundry fab to provide excellent customer service. Namely, ATDS provides fast and solid information to control each device shipment and enables manufacturing planner to change some system parameters to calculate out the capability of shipments. To sum up, ATDS is endowed with two-way, automaticity and accuracy to fit the demand of customers.
{"title":"Supply chain driven - advanced taget delivery system","authors":"Yih-Yi Lee, N. Fan","doi":"10.1109/SMTW.2004.1393704","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393704","url":null,"abstract":"How to build up a system to translate the quantity & delivery demand of customer to the manufacturing control in foundry fab which provides complex delivery service is the key for customer orientation - supply chain driven. Advanced target delivery system (ATDS) is the mechanism to translate the quantity & delivery demand of customer to the manufacturing control for pushing lots with accurate delivery according to MPSI of PC for foundry fabs. Function for monitoring the delivery status and perforate auto-change lot priority is a great contribution for foundry fab to provide excellent customer service. Namely, ATDS provides fast and solid information to control each device shipment and enables manufacturing planner to change some system parameters to calculate out the capability of shipments. To sum up, ATDS is endowed with two-way, automaticity and accuracy to fit the demand of customers.","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133530050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393757
Chia-Yu Hsu, Chen-Fu Chien, Yung-Chen Tsao, Cheng-Yi Li
Considering the limitations of the operation cost and the flexibility need of the manufacturing, the wafer was unable to expose in the same stepper from layer to layer in the real setting. In addition, the lithographic systems also require appreciate back-ups to avoid the yield loss as the equipment fault or shut-down for maintenance. This study aims to develop a machine group algorithm for the stepper and thus propose appropriate back-up based on the similarity of systematic overlay errors and residuals. The results are confirmed with judgments of domain experts and thus validated this approach
{"title":"Machine grouping algorithm for stepper back-up and an empirical study","authors":"Chia-Yu Hsu, Chen-Fu Chien, Yung-Chen Tsao, Cheng-Yi Li","doi":"10.1109/SMTW.2004.1393757","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393757","url":null,"abstract":"Considering the limitations of the operation cost and the flexibility need of the manufacturing, the wafer was unable to expose in the same stepper from layer to layer in the real setting. In addition, the lithographic systems also require appreciate back-ups to avoid the yield loss as the equipment fault or shut-down for maintenance. This study aims to develop a machine group algorithm for the stepper and thus propose appropriate back-up based on the similarity of systematic overlay errors and residuals. The results are confirmed with judgments of domain experts and thus validated this approach","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133354293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393750
Muh-Cherng Wu, C. Chien, K. Lu
This paper formulates a decision problem and proposes two solution methods for selecting the yield improvement alternatives in the test wafer recycle processes. The decision problem is to determine the yield improvement target for each recycle process in order to minimize the use of test wafers
{"title":"Planning yields in recycling test wafers","authors":"Muh-Cherng Wu, C. Chien, K. Lu","doi":"10.1109/SMTW.2004.1393750","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393750","url":null,"abstract":"This paper formulates a decision problem and proposes two solution methods for selecting the yield improvement alternatives in the test wafer recycle processes. The decision problem is to determine the yield improvement target for each recycle process in order to minimize the use of test wafers","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132474494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393734
Chia-Jen Chen, Hsin-Chang Lee, L. Yeh, Kai-Chung Liu, Ta-Cheng Lien, Yi-Chun Chuo, H. Hsieh, B. Lin
The specification of mask global CD uniformity (GCDU) is ever tightening. There is no exception at the 65-nm node. Some of the key contributors affecting GCD non-uniformity are pattern-density effects such as fagging effect from the e-beam writer and macro loading effect from the etcher. In addition, the contributions from position-dependent effects are significant, and these contributions included resist developing, baking, as well as aberrations of the wafer-imaging lens. It is challenging to quantify these effects and even more so to correct them to improve the GCDU. Correction of the fogging and etch loading effects had been reported by various authors. In addition to correction for these effects, we are reporting the position-dependent effects in this paper.
{"title":"Global CD uniformity improvement using dose modulation pattern correction of pattern density-dependent and position-dependent errors","authors":"Chia-Jen Chen, Hsin-Chang Lee, L. Yeh, Kai-Chung Liu, Ta-Cheng Lien, Yi-Chun Chuo, H. Hsieh, B. Lin","doi":"10.1109/SMTW.2004.1393734","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393734","url":null,"abstract":"The specification of mask global CD uniformity (GCDU) is ever tightening. There is no exception at the 65-nm node. Some of the key contributors affecting GCD non-uniformity are pattern-density effects such as fagging effect from the e-beam writer and macro loading effect from the etcher. In addition, the contributions from position-dependent effects are significant, and these contributions included resist developing, baking, as well as aberrations of the wafer-imaging lens. It is challenging to quantify these effects and even more so to correct them to improve the GCDU. Correction of the fogging and etch loading effects had been reported by various authors. In addition to correction for these effects, we are reporting the position-dependent effects in this paper.","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"516 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123090898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393760
C. Yu-Chih, K. L. Young, J.Y. Chou
The new technology, process control and cycle time management in semiconductor manufacturing for the R&D (research and development department) is import and is a great challenge task, because of the numerous engineering holds, lot splits, and necessary experimental processes are executing continued. The other challenge is an R&D pilot line exist large variety of process technologies. Therefore, short cycle time for new technology or process to meet customer demand is difficult but must to achieve the mission of the goal. Forecast this goal, we had kicked off a cooperation plan which name is `R&D cycle time system' with R&D members cooperate to complete it. In this paper, we present the system that includes six effective factors that they can easy to find symptoms on a long cycle time, a process or a technology issue by layer, stage or step. We give they name of these six key handling factors as x-ratio RD,x-ratio FAB,x-ratio RD, x-ratio FAB,f-factor and R1-factor . These measurements can judge whether delivered a lot on time on a layer, a stage or step and the process and technology is stable or unstable on it. Specially, the measurement value of f-factor and f1-factor can suggest a process step of technology is maturity or not. They like the eyes on this complex and changeful process flow of the R&D, this system hope to be a useful tool for supporting R&D member to find out the process, technology and cycle time issues about this kind of a tough question
{"title":"Key factor for new technology transfer on the R&D cycle-time system","authors":"C. Yu-Chih, K. L. Young, J.Y. Chou","doi":"10.1109/SMTW.2004.1393760","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393760","url":null,"abstract":"The new technology, process control and cycle time management in semiconductor manufacturing for the R&D (research and development department) is import and is a great challenge task, because of the numerous engineering holds, lot splits, and necessary experimental processes are executing continued. The other challenge is an R&D pilot line exist large variety of process technologies. Therefore, short cycle time for new technology or process to meet customer demand is difficult but must to achieve the mission of the goal. Forecast this goal, we had kicked off a cooperation plan which name is `R&D cycle time system' with R&D members cooperate to complete it. In this paper, we present the system that includes six effective factors that they can easy to find symptoms on a long cycle time, a process or a technology issue by layer, stage or step. We give they name of these six key handling factors as x-ratio RD,x-ratio FAB,x-ratio RD, x-ratio FAB,f-factor and R1-factor . These measurements can judge whether delivered a lot on time on a layer, a stage or step and the process and technology is stable or unstable on it. Specially, the measurement value of f-factor and f1-factor can suggest a process step of technology is maturity or not. They like the eyes on this complex and changeful process flow of the R&D, this system hope to be a useful tool for supporting R&D member to find out the process, technology and cycle time issues about this kind of a tough question","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116120900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393752
C. Liao, H.Y. Shao, Chien-Jung Liao, J. Hsu
The verified success of proton bombardment treatment in both the device isolation and the inductor Q-improvement (C. P. Liao et al., 2003) (C. P. Liao et al., 1998) on already-manufactured mixed-mode IC wafers (prior to packaging) has also uncovered new phenomena, especially the explosive rises of inductance near certain frequency (or, frequencies) (C. P. Liao et al., 2003). A previously proposed theory identified the cause to be resonant interaction between the inductor EM wave and the proton-caused defect electric dipoles (C. P. Liao et al., 2003). Based on such understanding, this paper aims at providing a new possibility of greatly enhancing the effectiveness of on-chip inductors by cushioning them on multiple dipoles using nanotechnical means
在已经制造的混合模式IC晶圆(在封装之前)上，质子轰击处理在器件隔离和电感器q改进(c.p. Liao et al.， 2003) (c.p. Liao et al.， 1998)方面的验证成功也揭示了新的现象，特别是在某些频率(或多个频率)附近电感的爆炸性上升(c.p. Liao et al.， 2003)。先前提出的理论认为，原因是电感器电磁波和质子引起的缺陷电偶极子之间的共振相互作用(c.p. Liao et al.， 2003)。基于这样的认识，本文旨在提供一种新的可能性，即利用纳米技术手段在多个偶极子上缓冲片上电感器，从而大大提高片上电感器的有效性
{"title":"On achieving large inductances for small on-chip inductors through providing pre-programmed multi-dipole cushioning for the spiral inductors via nano technology","authors":"C. Liao, H.Y. Shao, Chien-Jung Liao, J. Hsu","doi":"10.1109/SMTW.2004.1393752","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393752","url":null,"abstract":"The verified success of proton bombardment treatment in both the device isolation and the inductor Q-improvement (C. P. Liao et al., 2003) (C. P. Liao et al., 1998) on already-manufactured mixed-mode IC wafers (prior to packaging) has also uncovered new phenomena, especially the explosive rises of inductance near certain frequency (or, frequencies) (C. P. Liao et al., 2003). A previously proposed theory identified the cause to be resonant interaction between the inductor EM wave and the proton-caused defect electric dipoles (C. P. Liao et al., 2003). Based on such understanding, this paper aims at providing a new possibility of greatly enhancing the effectiveness of on-chip inductors by cushioning them on multiple dipoles using nanotechnical means","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"12 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131902691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393716
S. Chung, Ming-Hsiu Hsieh, Jui-Chun Liu
Wafer manufacturers usually face critical problems when making decisions regarding to the tool portfolio elimination, mainly due to the dramatic and frequent influences from their internal and external environments. This work is aimed to develop a mechanism, named tool portfolio elimination mechanism (TPEM), to evaluate the impacts on production performance and capital expenditure, and to determine which equipment is suitable for pruning. In TPEM, there are four stages to decide tool portfolio elimination according to the PDCA cycle. Meanwhile, the simulation results show that the fab production performance and cost are much improved by the TPEM algorithm. Especially, it can be applied and implemented to industry very quickly and easily.
{"title":"A tool portfolio elimination mechanism (TPEM) for a wafer fab","authors":"S. Chung, Ming-Hsiu Hsieh, Jui-Chun Liu","doi":"10.1109/SMTW.2004.1393716","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393716","url":null,"abstract":"Wafer manufacturers usually face critical problems when making decisions regarding to the tool portfolio elimination, mainly due to the dramatic and frequent influences from their internal and external environments. This work is aimed to develop a mechanism, named tool portfolio elimination mechanism (TPEM), to evaluate the impacts on production performance and capital expenditure, and to determine which equipment is suitable for pruning. In TPEM, there are four stages to decide tool portfolio elimination according to the PDCA cycle. Meanwhile, the simulation results show that the fab production performance and cost are much improved by the TPEM algorithm. Especially, it can be applied and implemented to industry very quickly and easily.","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123587656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-09-09DOI: 10.1109/SMTW.2004.1393764
Kochun Mou, Guang-Hann Chen
The importance of risk management in semiconductor industry is acknowledged by semiconductor industry. Risk management department should be independent to any other department and reports directly to top management (president) in the company. The organization of risk management should include (but not limit to) aspects of risk control, loss prevention, emergency response, insurance, industrial safety and health, environmental protection, medication, and security. Each section has its own tasks, however, they are not independent to one another. The tasks of each section and how they integrate each other are discussed in this study. Company would be impacted more or less when unexpected incident occurs. How company responds to the incident determine the severity of the impact. The role of risk management department in emergency response is also discussed in this study. The risk management system is tested and is operating in an existing semiconductor company and the performance is satisfactory.
{"title":"Risk management in semiconductor industry","authors":"Kochun Mou, Guang-Hann Chen","doi":"10.1109/SMTW.2004.1393764","DOIUrl":"https://doi.org/10.1109/SMTW.2004.1393764","url":null,"abstract":"The importance of risk management in semiconductor industry is acknowledged by semiconductor industry. Risk management department should be independent to any other department and reports directly to top management (president) in the company. The organization of risk management should include (but not limit to) aspects of risk control, loss prevention, emergency response, insurance, industrial safety and health, environmental protection, medication, and security. Each section has its own tasks, however, they are not independent to one another. The tasks of each section and how they integrate each other are discussed in this study. Company would be impacted more or less when unexpected incident occurs. How company responds to the incident determine the severity of the impact. The role of risk management department in emergency response is also discussed in this study. The risk management system is tested and is operating in an existing semiconductor company and the performance is satisfactory.","PeriodicalId":369092,"journal":{"name":"2004 Semiconductor Manufacturing Technology Workshop Proceedings (IEEE Cat. No.04EX846)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126381898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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