SRAM failure analysis evolution driven by technology scaling

Abstract

Demand for high speed and more function microelectronic devices has driven semiconductor industry to continue developing technologies with ever-shrinking geometry. During technology development, Static Random Access Memory (SRAM) is often chosen as the process qualification and yield learning vehicle. Thus SRAM failure analysis is the major activity in any microelectronic device failure analysis lab. Conventional physical failure analysis in old technology nodes has achieved high success rate since the SRAM bitcell failures can be precisely localized by functional test and the defect causing such failures is within the failing bitcells. However, As SRAM feature size decreases with technology scaling down, the size of the defect causing SRAM failure also scales down. Some of the defects are so tiny that they are invisible in ultra-high resolution SEM. On the other hand, the SRAM bitcell number greatly increases, and thus the SRAM design, especially address decoder scheme becomes more complex. More and complicated SRAM logic type failures arise. Therefore, the conventional physical failure analysis has faced increasing challenges and encountered low success rate. This paper will talk about how SRAM failure analysis evolves to maintain high success rate.