{"title":"2.9 A 29dBm 18.5% peak PAE mm-Wave digital power amplifier with dynamic load modulation","authors":"K. Datta, H. Hashemi","doi":"10.1109/ISSCC.2015.7062918","DOIUrl":null,"url":null,"abstract":"High speed, mm-Wave silicon transceivers with \"Watt-level\" output power have become necessary in recent years to support multi Gb/s communication protocols over realistic data-link lengths. However, efficient generation of power at mm-Waves is challenging in modern silicon processes with low breakdown voltages. Recent efforts have demonstrated \"Watt-level\" power generation using both silicon CMOS and HBT processes , but with <;10 % peak Power-Added-Efficiency (PAE) and without the ability to support modulation or power control efficiently. mm-Wave power DACs have been reported before, but with moderate output power (~ 24dBm) and low peak and average PAE (<;7%). This paper introduces a Watt-level mm-Wave digital power amplifier with significantly higher PAE at peak power level and back-off compared to existing state-of-the-art. Using highly efficient stacked Class-E amplifier unit cells, a 28.9dBm digital power amplifier is reported using a 0.13um SiGe HBT process with 18.4% peak PAE and 11% PAE at -6dB back-off with 8-level output amplitude control. Several innovative features like supply switch-less Class-E modulators to enable peak PAE, and a variable characteristic-impedance (Zchar) transmission-line-based dynamic load modulation network to maintain PAE under back-off have been demonstrated.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"326 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"28","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2015.7062918","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 28
Abstract
High speed, mm-Wave silicon transceivers with "Watt-level" output power have become necessary in recent years to support multi Gb/s communication protocols over realistic data-link lengths. However, efficient generation of power at mm-Waves is challenging in modern silicon processes with low breakdown voltages. Recent efforts have demonstrated "Watt-level" power generation using both silicon CMOS and HBT processes , but with <;10 % peak Power-Added-Efficiency (PAE) and without the ability to support modulation or power control efficiently. mm-Wave power DACs have been reported before, but with moderate output power (~ 24dBm) and low peak and average PAE (<;7%). This paper introduces a Watt-level mm-Wave digital power amplifier with significantly higher PAE at peak power level and back-off compared to existing state-of-the-art. Using highly efficient stacked Class-E amplifier unit cells, a 28.9dBm digital power amplifier is reported using a 0.13um SiGe HBT process with 18.4% peak PAE and 11% PAE at -6dB back-off with 8-level output amplitude control. Several innovative features like supply switch-less Class-E modulators to enable peak PAE, and a variable characteristic-impedance (Zchar) transmission-line-based dynamic load modulation network to maintain PAE under back-off have been demonstrated.