Session T1A: Tutorial: Phase-locked clock generation for SoC: Circuit and system design aspects

Abstract

A phase-locked loop is a key building block in wireline and wireless systems. In the wireline systems, low-jitter clock generation and versatile clock-and-data recovery circuits are critical in high data rate I/O links. In the wireless systems, the DS PLL based synthesizer plays a critical role in modern transceivers not only as a local oscillator but also as a phase modulator with direct digital modulation. However, the traditional PLL in advanced CMOS technology suffers from poor scalability, loop parameter variability and leakage current problems. Accordingly, diversified PLL architectures and circuit techniques have been recently proposed in consideration of performance, power and cost, thus making it more difficult for circuit designers to choose the right design solution than ever. This tutorial gives some insight into PLL basics tailored for circuit designers. Then, system perspectives and practical circuit design aspects will be presented. Furthermore, various PLL architectures and design challenges will be discussed.