Analysis and comparison of fault tolerant FSM architecture based on SEC codes

Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1993-10-27 DOI:10.1109/DFTVS.1993.595604

R. Rochet, R. Leveugle, G. Saucier

引用次数: 17

Abstract

Implementing single fault tolerant finite state machines (FSMs) in VLSI circuits might be done using triplication and voting (TMR). Alternatives are based on the use of an error correcting (SEC) code during the state assignment. Such architectures are studied and their characteristics are analyzed for a set of international and industrial FSM benchmarks. The results demonstrate that one of these architectures leads in some cases to implementation with less hardware overhead than TMR and should actually be considered for some types of circuits.

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基于SEC代码的FSM容错体系结构分析与比较

在VLSI电路中实现单容错有限状态机(FSMs)可以使用三乘和投票(TMR)来实现。备选方案基于在状态分配期间使用的错误纠正(SEC)代码。本文研究了这种体系结构，并分析了它们的特点，以作为一组国际和工业FSM基准。结果表明，在某些情况下，这些架构中的一种可以实现比TMR更少的硬件开销，并且实际上应该考虑用于某些类型的电路。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

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