A model for enhanced manufacturability of defect tolerant integrated circuits

Abstract

Many factors contribute the the cost of manufacturing integrated circuits. These include the yield of the design IC, the complexity of its testing, the packaging cost, etc. and they all must be taken into account when designing a defect tolerant integrated circuit. The authors present a mathematical model which includes all major factors contributing to the cost of manufacturing ICs. This model allows the determination of the design which maximizes the expected profit rather than maximizing the yield. Numerical examples illustrating the proposed model are also presented.<>