A Compact and Broadband On-Chip Delay Line Design Based on the Bridged T-Coil

Abstract

This paper presents a design approach for on-chip realization of compact and broadband delay units based on the bridged T-coil. Closed-form design equations for the bridged T-coil circuit elements are derived from the 2nd order Padé approximation. Standardized delay units are designed having high isolation from adjacent circuitry by use of a guard ring. The main layout parasitics are incorporated into the design and a detailed design procedure together with a parasitic circuit model is presented. Two delay units for 20-ps and 30-ps delay are designed in a TowerSemi 0.18μm SiGe BiCMOS process to demonstrate the design approach. Full-wave electromagnetic simulations demonstrate the flatness of the group delay responses up to 13 GHz for the 20-ps delay and up to 8 GHz for the 30-ps delay, exceeding the bandwidths obtained with the Padé approximation design with negligible increase in insertion loss and negligible ripple in the flat group delay region. The maximum insertion loss in the region with flat group delay is less than 1dB.