The off leakage in SOI-MOS transistors and the impact on the standby current of ULSI's

A. Adan, K. Higashi, K. Nimi, T. Ashida
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引用次数: 2

Abstract

Summary form only given. The application of SOI-CMOS to low-voltage, battery-powered devices is facing the practical trade-off between low threshold voltage and off-state leakage current. For typical portable electronic equipment, the specification for standby power dissipation restricts the MOSFET off-current to I/sub doff/<10 pA//spl mu/m, which should be compared with I/sub doff//spl sim/1 nA//spl mu/m in high-speed microprocessors (Leonbandung et al., 1998). In this paper, we investigate the off-current mechanism in SOI MOSFETs and its relationship with the IC's standby current for quantitative modeling. The model parameter extraction techniques are also described.
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SOI-MOS晶体管的漏关及其对ULSI待机电流的影响
只提供摘要形式。SOI-CMOS在低压电池供电器件中的应用,面临着低阈值电压和断态泄漏电流之间的实际权衡。对于典型的便携式电子设备,待机功耗规范将MOSFET的关断电流限制在I/sub - off/<10 pA//spl mu/m,应与高速微处理器的I/sub - off//spl sim/1 nA//spl mu/m进行比较(Leonbandung et al., 1998)。在本文中,我们研究了SOI mosfet的断流机制及其与IC待机电流的关系,以进行定量建模。并介绍了模型参数提取技术。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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