Defect mode classification in logic LSI manufacturing process using I/sub DDQ/

Abstract

Abnormal I/sub DDQ/ (Quiescent V/sub DD/ supply current) indicates the existence of physical damage in a circuit Using this phenomenon, a CAD-based fault diagnosis technology has been developed to analyze the manufacturing yield of logic LSI. This method to detect the fatal defect fragments in several abnormalities identified with wafer inspection apparatus includes a way to separate various leakage faults and to define the diagnosis area encircling the abnormal portions. The diagnosis way progressively narrows the faulty area by using logic simulation to extract the logic states of the diagnosis area, and by locating test vectors related to abnormal I/sub DDQ/. The fundamental diagnosis way employs the comparative operation of each circuit. The obtained result is investigated to analyze the manufacturing process which mostly influences yield and to classify the fault mode. These defect information is fed back to logic LSI manufacturing processes, helping to improve manufacturing yield.