Pub Date : 2000-12-01DOI: 10.1109/ISSM.2000.993630
C. Hayzelden, C. Ygartua, T. Casavant, M. Slessor, A. Srivatsa, M. Guévremont, P. Stevens, M. Young, T. Lu, R. Zhang, C. Treadwell, D. Soltz, J. Lauber, M. Krumbuegel, R. Fiordalice, S. Lange, R. Marella, S. Ashkenaz, K. Monahan, T. K. Tran, J. Leu
A process control system is composed of a variety of elements, from measurement technologies and techniques, through sampling strategies and analysis algorithms, to data-driven action plans. All components are required to ensure a stable process, however, effective control is founded upon a set of easily measured, yield-relevant parameters. In this work, we describe the use of a toolset and methodology to provide such parameters, and explore sampling and analysis components for the evaluation, development, and control of low-/spl kappa/ dielectric processes. In comparison to historically-employed interline dielectric (ILD) materials such as SiO/sub 2/, these low-/spl kappa/ materials and processes present significant integration, reliability, and stability concerns. A particularly sensitive parameter is the dielectric constant itself. Damage from high-power ultraviolet inspection techniques may also present challenges. As these relatively immature processes migrate into volume production, these same tools and parameters can be used to monitor the low-/spl kappa/ process module, improve baseline yield, and control excursions.
{"title":"Process module control for low-/spl kappa/ dielectrics [CVD]","authors":"C. Hayzelden, C. Ygartua, T. Casavant, M. Slessor, A. Srivatsa, M. Guévremont, P. Stevens, M. Young, T. Lu, R. Zhang, C. Treadwell, D. Soltz, J. Lauber, M. Krumbuegel, R. Fiordalice, S. Lange, R. Marella, S. Ashkenaz, K. Monahan, T. K. Tran, J. Leu","doi":"10.1109/ISSM.2000.993630","DOIUrl":"https://doi.org/10.1109/ISSM.2000.993630","url":null,"abstract":"A process control system is composed of a variety of elements, from measurement technologies and techniques, through sampling strategies and analysis algorithms, to data-driven action plans. All components are required to ensure a stable process, however, effective control is founded upon a set of easily measured, yield-relevant parameters. In this work, we describe the use of a toolset and methodology to provide such parameters, and explore sampling and analysis components for the evaluation, development, and control of low-/spl kappa/ dielectric processes. In comparison to historically-employed interline dielectric (ILD) materials such as SiO/sub 2/, these low-/spl kappa/ materials and processes present significant integration, reliability, and stability concerns. A particularly sensitive parameter is the dielectric constant itself. Damage from high-power ultraviolet inspection techniques may also present challenges. As these relatively immature processes migrate into volume production, these same tools and parameters can be used to monitor the low-/spl kappa/ process module, improve baseline yield, and control excursions.","PeriodicalId":104122,"journal":{"name":"Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123811881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/ISSM.2000.993626
R. Kaihara, M. Hirayama, S. Sugawa, T. Ohmil
A new plasma source called balanced electron drift (BED) magnetron plasma has been developed for SiO/sub 2/ contact/via hole etching. E/spl times/B drift of electrons, which is notorious for degrading the uniformity of magnetron plasmas, has been completely balanced by applying appropriate 100 MHz rf power to the upper ring electrode. As a result, charge-up damage free and highly uniform etch rate of /spl plusmn/2.72% profiles were obtained on 200 mm wafer. Micro-loading effect free etching was also achieved by suppressing excess dissociation of C/sub 4/F/sub 8/. The BED magnetron etcher has an additional benefit of reducing dopant deactivation in the Si substrate because carbon-rich fluorocarbon film can protect the Si surface from high-energy ion bombardment during the over-etch period. Also, the addition of Xe has been confirmed to exhibit drastic suppression of the dopant deactivation even at p/sup +/Si surface, which results in low contact resistance without additional ion implantation after the contact etch. The BED magnetron etcher using Xe gas can reduce a few tens of process steps after the contact etch.
{"title":"Damage-free contact etching using balanced electron drift magnetron etcher","authors":"R. Kaihara, M. Hirayama, S. Sugawa, T. Ohmil","doi":"10.1109/ISSM.2000.993626","DOIUrl":"https://doi.org/10.1109/ISSM.2000.993626","url":null,"abstract":"A new plasma source called balanced electron drift (BED) magnetron plasma has been developed for SiO/sub 2/ contact/via hole etching. E/spl times/B drift of electrons, which is notorious for degrading the uniformity of magnetron plasmas, has been completely balanced by applying appropriate 100 MHz rf power to the upper ring electrode. As a result, charge-up damage free and highly uniform etch rate of /spl plusmn/2.72% profiles were obtained on 200 mm wafer. Micro-loading effect free etching was also achieved by suppressing excess dissociation of C/sub 4/F/sub 8/. The BED magnetron etcher has an additional benefit of reducing dopant deactivation in the Si substrate because carbon-rich fluorocarbon film can protect the Si surface from high-energy ion bombardment during the over-etch period. Also, the addition of Xe has been confirmed to exhibit drastic suppression of the dopant deactivation even at p/sup +/Si surface, which results in low contact resistance without additional ion implantation after the contact etch. The BED magnetron etcher using Xe gas can reduce a few tens of process steps after the contact etch.","PeriodicalId":104122,"journal":{"name":"Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116836410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/ISSM.2000.993667
S. P. Papa Rao, R. Guldi, J. Garvin, S. Lavangkul, D. Curran, R. Worley, J. Hightower
Yield enhancement techniques for the latest generation of devices need sensitive inspection recipes in order to detect the ever-smaller defects that can result in yield loss. Offline analysis techniques (using MATLAB, for example) for the improvement of bright-field defect-inspection tool recipes are presented. Simple techniques are given for the rapid incorporation or modification of care-areas/don't-care areas into pre-existing recipes. Postprocessing analyses of defect data are presented to show their efficacy in improving the signal-to-noise ratio for defects that might otherwise be hidden in the noise created by 'nuisance' defects. Examples are presented to show how design-databases and reticle inspection data can be harnessed in understanding defect mechanisms.
{"title":"Offline analysis techniques for the improvement of defect inspection recipes","authors":"S. P. Papa Rao, R. Guldi, J. Garvin, S. Lavangkul, D. Curran, R. Worley, J. Hightower","doi":"10.1109/ISSM.2000.993667","DOIUrl":"https://doi.org/10.1109/ISSM.2000.993667","url":null,"abstract":"Yield enhancement techniques for the latest generation of devices need sensitive inspection recipes in order to detect the ever-smaller defects that can result in yield loss. Offline analysis techniques (using MATLAB, for example) for the improvement of bright-field defect-inspection tool recipes are presented. Simple techniques are given for the rapid incorporation or modification of care-areas/don't-care areas into pre-existing recipes. Postprocessing analyses of defect data are presented to show their efficacy in improving the signal-to-noise ratio for defects that might otherwise be hidden in the noise created by 'nuisance' defects. Examples are presented to show how design-databases and reticle inspection data can be harnessed in understanding defect mechanisms.","PeriodicalId":104122,"journal":{"name":"Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128715374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/ISSM.2000.993646
J. Segal, S. Parker, S. Bakarian, J. Pak
Critical area analysis was performed on a complex microprocessor design. (>1 Gbyte GDS file). The following applications of critical area analysis are demonstrated: yield partitioning by process layer, yield partitioning by layout block, and design for manufacturability. Advanced features such as netlist extraction, layer shift operation, and geometric expansion compared to Monte Carlo critical area extraction are discussed.
{"title":"Critical area based yield modeling on an advanced microprocessor design","authors":"J. Segal, S. Parker, S. Bakarian, J. Pak","doi":"10.1109/ISSM.2000.993646","DOIUrl":"https://doi.org/10.1109/ISSM.2000.993646","url":null,"abstract":"Critical area analysis was performed on a complex microprocessor design. (>1 Gbyte GDS file). The following applications of critical area analysis are demonstrated: yield partitioning by process layer, yield partitioning by layout block, and design for manufacturability. Advanced features such as netlist extraction, layer shift operation, and geometric expansion compared to Monte Carlo critical area extraction are discussed.","PeriodicalId":104122,"journal":{"name":"Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124107302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/ISSM.2000.993662
V. Atluri, L.M. Dass, K. Seshan, K.C. Patel, R. Stage, TP Alexander, T. Dory, S. Balakrishnan
In this paper we present the results related to thermomechanical failures (TMF) in silicon integrated circuits assembled in plastic packages. Damage to silicon was believed to be caused by the thermal mismatch stress due to large difference in coefficients of thermal expansion between silicon die and plastic assembly package. The damage was primarily concentrated at the comer of the unit and was considered as a high risk compromising reliability. In order to address the TMF damage to silicon, different structures such as metal locking structures, guard ring modification, slotting assembly fiducials and elimination of passivation at the scribe street were studied Silicon incorporating the structures was assembled in plastic packages and reliability tested. All the units were electrical tested. The results showed that the scribe street passivation and fab process alignment marks play a key role during assembly saw process and related TMF performance. Visual inspections were performed to understand the effect of nitride passivation thickness, package stiffness, and thermal cycling stresses on TMF damage induced on Si devices assembled in Organic Land Grid Array (OLGA) packages.
{"title":"Thermomechanical failures in silicon electronic devices","authors":"V. Atluri, L.M. Dass, K. Seshan, K.C. Patel, R. Stage, TP Alexander, T. Dory, S. Balakrishnan","doi":"10.1109/ISSM.2000.993662","DOIUrl":"https://doi.org/10.1109/ISSM.2000.993662","url":null,"abstract":"In this paper we present the results related to thermomechanical failures (TMF) in silicon integrated circuits assembled in plastic packages. Damage to silicon was believed to be caused by the thermal mismatch stress due to large difference in coefficients of thermal expansion between silicon die and plastic assembly package. The damage was primarily concentrated at the comer of the unit and was considered as a high risk compromising reliability. In order to address the TMF damage to silicon, different structures such as metal locking structures, guard ring modification, slotting assembly fiducials and elimination of passivation at the scribe street were studied Silicon incorporating the structures was assembled in plastic packages and reliability tested. All the units were electrical tested. The results showed that the scribe street passivation and fab process alignment marks play a key role during assembly saw process and related TMF performance. Visual inspections were performed to understand the effect of nitride passivation thickness, package stiffness, and thermal cycling stresses on TMF damage induced on Si devices assembled in Organic Land Grid Array (OLGA) packages.","PeriodicalId":104122,"journal":{"name":"Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)","volume":" 13","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120828942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/ISSM.2000.993607
R. J. Montoya, G. Williams
The collective output of multiple high volume factories located around the world has enabled Intel to satisfy the enormous demand requirements of customers worldwide. The global operation concept transforms this cooperation barrier into a strategic advantage by sharing resources to improve engineering support of Intel's global manufacturing operation. The concept capitalizes on e-manufacturing concepts and Intel's "copy exactly methodology", which ensure that factories have virtually identical infrastructure. Downtime events that require engineering support can be handled by engineering support from any of Intel identical factories. Downtime incidents are automatically routed to the appropriate engineer worldwide. It also gives them the ability to remotely access and control tools from other factories. This technology allows virtually any issue that requires engineering support to be solved remotely. Typically, to reduce the potential downtime impact, downtime events are handled by engineers on-call. The concept is being expanded into many different engineering functions and among additional factories to further increase the hours of on-site engineering coverage. This paper describes the benefits and challenges involved with implementing this concept at Intel.
{"title":"Transforming Intel factories from global presence to global operation!","authors":"R. J. Montoya, G. Williams","doi":"10.1109/ISSM.2000.993607","DOIUrl":"https://doi.org/10.1109/ISSM.2000.993607","url":null,"abstract":"The collective output of multiple high volume factories located around the world has enabled Intel to satisfy the enormous demand requirements of customers worldwide. The global operation concept transforms this cooperation barrier into a strategic advantage by sharing resources to improve engineering support of Intel's global manufacturing operation. The concept capitalizes on e-manufacturing concepts and Intel's \"copy exactly methodology\", which ensure that factories have virtually identical infrastructure. Downtime events that require engineering support can be handled by engineering support from any of Intel identical factories. Downtime incidents are automatically routed to the appropriate engineer worldwide. It also gives them the ability to remotely access and control tools from other factories. This technology allows virtually any issue that requires engineering support to be solved remotely. Typically, to reduce the potential downtime impact, downtime events are handled by engineers on-call. The concept is being expanded into many different engineering functions and among additional factories to further increase the hours of on-site engineering coverage. This paper describes the benefits and challenges involved with implementing this concept at Intel.","PeriodicalId":104122,"journal":{"name":"Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132470785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/ISSM.2000.993679
K. Tsukamoto, T. Mizuniwa, J. Ida, O. Ota, I. Morita
A new ozonated ultrapure water (O/sub 3/-UPW) supplying system has been established. In the new O/sub 3/-UPW supplying system, a direct dissolving method that can supply O/sub 3/-UPW to many separated points of use from a single unit has been employed. In this system, ozone-containing gas is directly introduced in ultrapure water (direct dissolving) and the water/gas mixture is transported to many points of use through a piping system. At each point of use, bubbles in water/gas mixture are separated and O/sub 3/-UPW without bubbles is supplied to the cleaning equipment. The concentration of dissolved ozone in water rapidly decreases because of self-decomposition. On the other hand ozone in the gas phase is more stable than in the water phase and ozone in the bubbles (gas phase) becomes dissolved in the water while transported through the piping system. As a result; O/sub 3/-UPW with the ozone concentration of higher than 5 ppm is supplied to the cleaning equipment that is installed at distant places as far as 100 m from ozone gas introducing point. We have provided the new system in one of the latest LCD fabrication plants, which is presently in operation.
{"title":"Development of ozonated ultrapure water supplying system using direct-dissolving method","authors":"K. Tsukamoto, T. Mizuniwa, J. Ida, O. Ota, I. Morita","doi":"10.1109/ISSM.2000.993679","DOIUrl":"https://doi.org/10.1109/ISSM.2000.993679","url":null,"abstract":"A new ozonated ultrapure water (O/sub 3/-UPW) supplying system has been established. In the new O/sub 3/-UPW supplying system, a direct dissolving method that can supply O/sub 3/-UPW to many separated points of use from a single unit has been employed. In this system, ozone-containing gas is directly introduced in ultrapure water (direct dissolving) and the water/gas mixture is transported to many points of use through a piping system. At each point of use, bubbles in water/gas mixture are separated and O/sub 3/-UPW without bubbles is supplied to the cleaning equipment. The concentration of dissolved ozone in water rapidly decreases because of self-decomposition. On the other hand ozone in the gas phase is more stable than in the water phase and ozone in the bubbles (gas phase) becomes dissolved in the water while transported through the piping system. As a result; O/sub 3/-UPW with the ozone concentration of higher than 5 ppm is supplied to the cleaning equipment that is installed at distant places as far as 100 m from ozone gas introducing point. We have provided the new system in one of the latest LCD fabrication plants, which is presently in operation.","PeriodicalId":104122,"journal":{"name":"Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125204673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/ISSM.2000.993648
A. Shimoda, K. Watanabe, Y. Takagi, S. Maeda
We present a systematic yield ramp-up method that can quickly screen "killer" particles associated with yield loss and pinpoint their entry point to the process. The proposed method uses automatic defect classification (ADC) to segregate killer particles. The practicality of this method is demonstrated by the results of experiments using actual production wafers. This method will make killer particle control more timely.
{"title":"Short cycle killer-particle control based on accurate in-line defect classification","authors":"A. Shimoda, K. Watanabe, Y. Takagi, S. Maeda","doi":"10.1109/ISSM.2000.993648","DOIUrl":"https://doi.org/10.1109/ISSM.2000.993648","url":null,"abstract":"We present a systematic yield ramp-up method that can quickly screen \"killer\" particles associated with yield loss and pinpoint their entry point to the process. The proposed method uses automatic defect classification (ADC) to segregate killer particles. The practicality of this method is demonstrated by the results of experiments using actual production wafers. This method will make killer particle control more timely.","PeriodicalId":104122,"journal":{"name":"Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)","volume":"233 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123665890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/ISSM.2000.993692
H. Hasegawa, T. Yamaoka, M. Hamano, Y. Ishihara, T. Satoh
In epitaxial process, halide and hydrogen halide gases are used as a source gas or chamber cleaning gas. These gases are very corrosive in the presence of moisture. Hence, metal contamination will be very severe problem, if moisture get into epitaxial process. So we investigated the behavior of moisture gotten into the epitaxial process chamber and the relationship between moisture concentration and metal contamination. As a result, they became clear that moisture in the process chamber is promptly adsorbed on the inner surface of the process chamber and it does not leave easily except for HCl gas atmosphere, and that metal contamination level relates to moisture concentration. Therefore, the moisture monitoring and controlling can reduce the frequency of ex-situ metal inspection such as SIMS, SPV and DLTS. The improvement of the throughput is also expected because of inspection time reduction and quick startup after maintenance. The moisture monitoring with spectrometer could be very effective on both cost and quality.
{"title":"Improvement in throughput of silicon epitaxial process by using in-line moisture monitoring","authors":"H. Hasegawa, T. Yamaoka, M. Hamano, Y. Ishihara, T. Satoh","doi":"10.1109/ISSM.2000.993692","DOIUrl":"https://doi.org/10.1109/ISSM.2000.993692","url":null,"abstract":"In epitaxial process, halide and hydrogen halide gases are used as a source gas or chamber cleaning gas. These gases are very corrosive in the presence of moisture. Hence, metal contamination will be very severe problem, if moisture get into epitaxial process. So we investigated the behavior of moisture gotten into the epitaxial process chamber and the relationship between moisture concentration and metal contamination. As a result, they became clear that moisture in the process chamber is promptly adsorbed on the inner surface of the process chamber and it does not leave easily except for HCl gas atmosphere, and that metal contamination level relates to moisture concentration. Therefore, the moisture monitoring and controlling can reduce the frequency of ex-situ metal inspection such as SIMS, SPV and DLTS. The improvement of the throughput is also expected because of inspection time reduction and quick startup after maintenance. The moisture monitoring with spectrometer could be very effective on both cost and quality.","PeriodicalId":104122,"journal":{"name":"Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124030447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-26DOI: 10.1109/ISSM.2000.993686
H. Ozaki, K. Yatnana, Y. Matsuo, T. Murakami, T. Yamamo, K. Morimoto, A. Shigetomi
To realize an efficient pre-production line, we developed "Autonomic Information System for modern LSIs " (AIS). This system is combined with yield management system (YMS) and manufacturing management system (Fab Host) by using personal computers. It distributes visual information about loss-time of bottleneck equipment on production clearly and a particle map with background data for each lot and each process. By using this information system, all the concerned persons (line manager, engineers and technicians) can dissolve problems independently, appropriately and quickly like the autonomic nervous system works in the human body. "AIS" has been developing in our R&D pilot line as a loss-time reduction tool.
{"title":"Autonomic information system for pre-production of modern LSIs","authors":"H. Ozaki, K. Yatnana, Y. Matsuo, T. Murakami, T. Yamamo, K. Morimoto, A. Shigetomi","doi":"10.1109/ISSM.2000.993686","DOIUrl":"https://doi.org/10.1109/ISSM.2000.993686","url":null,"abstract":"To realize an efficient pre-production line, we developed \"Autonomic Information System for modern LSIs \" (AIS). This system is combined with yield management system (YMS) and manufacturing management system (Fab Host) by using personal computers. It distributes visual information about loss-time of bottleneck equipment on production clearly and a particle map with background data for each lot and each process. By using this information system, all the concerned persons (line manager, engineers and technicians) can dissolve problems independently, appropriately and quickly like the autonomic nervous system works in the human body. \"AIS\" has been developing in our R&D pilot line as a loss-time reduction tool.","PeriodicalId":104122,"journal":{"name":"Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126014568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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