Wave monitor for glitch detection and skew adjusting in high-speed DAC

Kojiro Tokonami, Kaoru Kohira, H. Ishikuro
{"title":"Wave monitor for glitch detection and skew adjusting in high-speed DAC","authors":"Kojiro Tokonami, Kaoru Kohira, H. Ishikuro","doi":"10.1109/RFIT.2015.7377925","DOIUrl":null,"url":null,"abstract":"In this paper, a high-speed current steering DAC with wave monitor circuit is proposed. Comparator-based wave monitor circuit makes it possible to detect a glitch and adjust the skew of each bit digital signal. Fabricated test chip in 40nm-CMOS demonstrates the performance improvement by glitch detection and skew adjusting. At 1GS/sec, the fabricated DAC achieved ENOB of 5.17 bit and power consumption of 2.38mW.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIT.2015.7377925","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

Abstract

In this paper, a high-speed current steering DAC with wave monitor circuit is proposed. Comparator-based wave monitor circuit makes it possible to detect a glitch and adjust the skew of each bit digital signal. Fabricated test chip in 40nm-CMOS demonstrates the performance improvement by glitch detection and skew adjusting. At 1GS/sec, the fabricated DAC achieved ENOB of 5.17 bit and power consumption of 2.38mW.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
用于高速DAC中的故障检测和倾斜调整的波监测器
本文提出了一种带波形监测电路的高速电流转向数模转换器。基于比较器的波形监测电路使检测故障和调整每位数字信号的斜度成为可能。在40nm cmos上制作的测试芯片通过毛刺检测和倾斜调节来提高性能。在1GS/秒的速度下,所制造的DAC实现了5.17位的ENOB和2.38mW的功耗。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
High-speed III-V devices for millimeter-wave receiver applications (Invited) A low-power high-Q matching LNA with small-size matching calibration circuit for low power receiver A low noise amplifier with coupled matching structure for V-band applications Cryogenic low noise amplifier for phased array antenna A 76–81 GHz high efficiency power amplifier for phased array automotive radar applications
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1