MOS current mode logic: design, optimization, and variability

IEEE International SOC Conference, 2004. Proceedings. Pub Date : 2004-11-30 DOI:10.1109/SOCC.2004.1362424

Hassan Hassan, M. Anis, M. Elmasry

引用次数: 14

Abstract

An automated optimization-based design strategy for 2-level MOS current mode logic (MCML) circuits is proposed to overcome the complexities of the design process. The methodology minimizes the power dissipation while satisfying the performance criteria. Moreover, environmental and process variations modeling are included in the design strategy. The impact of these variations on MCML performance as technology scales is also presented. In addition, design tips based on analytic formulation are presented for MCML designers. The proposed methodology is tested on several benchmarks belonging to optical communication and high-speed microprocessor applications built in a CMOS 0.18/spl mu/m process, at which the average error is within 7% between our formulation and HSPICE.

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MOS电流模式逻辑:设计、优化和可变性

针对2级MOS电流模逻辑电路设计过程的复杂性，提出了一种基于自动优化的设计策略。该方法在满足性能标准的同时最大限度地降低了功耗。此外，设计策略中还包括环境和过程变化建模。随着技术规模的扩大，这些变化对MCML性能的影响也会出现。此外，本文还为MCML设计人员提供了基于解析公式的设计技巧。所提出的方法在几个属于光通信和高速微处理器应用的基准测试中进行了测试，这些应用基于CMOS 0.18/spl mu/m工艺，我们的配方与HSPICE之间的平均误差在7%以内。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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IEEE International SOC Conference, 2004. Proceedings.

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