Impact of low temperature on the TSG Vt shift during erase cycling of 3-D NAND Flash memory

Da Li, Z. Huo, Jianhua Feng, Lei Jin, Liang Yan, Xinlei Jia, Jianquan Jia, Yali Song, An Zhang, Feng Xu, Wei Hou
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引用次数: 1

Abstract

Charge trapping memory (CTM) endurance has been widely investigated in recent years. Most studies are focused on array cell Vt instabilities, which is originated from charge trapping/detrapping in cell tunnel oxide and interface traps. Our previous works demonstrate erase only cycling induced TSG shift in 3D NAND flash. In this work, it is found that the erase cycling induced TSG VT shift is temperature dependent. TSG Vt shift under low temperature is obviously worse than room and high temperature. TCAD simulation shows hot carrier induced by channel potential gradient is more significant under low temperature during erase operation due to low mobility. The stability of TSG cell Vt is related with both temperature and TSG bias voltage during erase according to the experiments and simulation.
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低温对3-D NAND闪存擦除循环中TSG Vt位移的影响
电荷捕获记忆(CTM)的持久性能近年来得到了广泛的研究。大多数研究集中在阵列电池的Vt不稳定性上,它源于电池隧道氧化物和界面陷阱中的电荷捕获/去捕获。我们之前的工作证明了仅擦除循环引起的3D NAND闪存的TSG移位。在这项工作中,发现擦除循环诱导的TSG - VT位移与温度有关。低温下的TSG位移明显差于室温和高温。TCAD仿真结果表明,由于低迁移率,在低温条件下擦除过程中通道电位梯度引起的热载流子效应更为显著。实验和仿真结果表明,擦除过程中TSG单元Vt的稳定性与温度和TSG偏置电压有关。
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