Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984823
Ching-Chun Lin, Kim Hsu
A novel approach to detect the crystal defects extended along particular orientation using differential phase contrast (DPC) images with segmented type detector for wide range of devices and materials in scanning transmission electron microscope (STEM) is provided. In addition, the signals from different segments could be further processed to enhance the contrast of light elements specifically, which also called enhanced annular bright field (eABF) mode in segmented annular all field (SAAF) system.
{"title":"Defect Characterization by Differential Phase Contrast Imaging Technique in Scanning Transmission Electron Microscope","authors":"Ching-Chun Lin, Kim Hsu","doi":"10.1109/IPFA47161.2019.8984823","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984823","url":null,"abstract":"A novel approach to detect the crystal defects extended along particular orientation using differential phase contrast (DPC) images with segmented type detector for wide range of devices and materials in scanning transmission electron microscope (STEM) is provided. In addition, the signals from different segments could be further processed to enhance the contrast of light elements specifically, which also called enhanced annular bright field (eABF) mode in segmented annular all field (SAAF) system.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123104442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984881
Weiwei Zhang, Yuanxin Lee, Yi Zhang
Creep corrosion classically happens on PCBs and PCBAs working in Sulfur-rich environment with humidity. Copper and silver metallization on PCB aand PCBA could be corroded by Sulfur-base gases. The associated corrosion products can creep to adjacent circuits, making electrical short failure of the system due to closely spaced metallized features on PCBs and PCBAs. This paper will introduce a novel creep corrosion failure of a SOP IC on power module. We found that a serial of flaws of the SOP package could be the original point of creep corrosion between adjacent pins. Finally, a serial of corrective methods was proposed to mitigate the creep corrosion problem on this SOP component.
{"title":"A Failure Analysis of a SOP IC Creep Corrosion on power module","authors":"Weiwei Zhang, Yuanxin Lee, Yi Zhang","doi":"10.1109/IPFA47161.2019.8984881","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984881","url":null,"abstract":"Creep corrosion classically happens on PCBs and PCBAs working in Sulfur-rich environment with humidity. Copper and silver metallization on PCB aand PCBA could be corroded by Sulfur-base gases. The associated corrosion products can creep to adjacent circuits, making electrical short failure of the system due to closely spaced metallized features on PCBs and PCBAs. This paper will introduce a novel creep corrosion failure of a SOP IC on power module. We found that a serial of flaws of the SOP package could be the original point of creep corrosion between adjacent pins. Finally, a serial of corrective methods was proposed to mitigate the creep corrosion problem on this SOP component.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127167391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984898
Haochun Fu, Jiaxing Wei, Siyang Liu, Wangran Wu, Weifeng Sun
Repetitive avalanche stress results in the injection of hot holes into the gate oxide interface, which leads to the degradations of electrical parameters, attracting wide attentions on improving the avalanche reliability of SiC power MOSFETs. A high avalanche reliability structure with two additional step gate oxides is then proposed in this work. With the help of Silvaco TCAD simulations, the optimized width and thickness of the additional oxides are determined. When compared with the conventional device structure, it is found that the peaks of perpendicular electric field and impact ionization rate of the improved structure under avalanche status are respectively reduced by 10% and 51%. Meanwhile, the breakdown voltage and the on-state resistance of the device are almost unchanged. Therefore, the improved device structure can effectively suppress the degradations caused by avalanche stress.
{"title":"Repetitive-avalanche-induced Electrical Degradation and Optimization for 1.2kV 4H-SiC MOSFETs","authors":"Haochun Fu, Jiaxing Wei, Siyang Liu, Wangran Wu, Weifeng Sun","doi":"10.1109/IPFA47161.2019.8984898","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984898","url":null,"abstract":"Repetitive avalanche stress results in the injection of hot holes into the gate oxide interface, which leads to the degradations of electrical parameters, attracting wide attentions on improving the avalanche reliability of SiC power MOSFETs. A high avalanche reliability structure with two additional step gate oxides is then proposed in this work. With the help of Silvaco TCAD simulations, the optimized width and thickness of the additional oxides are determined. When compared with the conventional device structure, it is found that the peaks of perpendicular electric field and impact ionization rate of the improved structure under avalanche status are respectively reduced by 10% and 51%. Meanwhile, the breakdown voltage and the on-state resistance of the device are almost unchanged. Therefore, the improved device structure can effectively suppress the degradations caused by avalanche stress.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127314444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Latch-Up is a common circuit design problem in product reliability. Because of the poor design of the integrated circuit, the P-N-P-N junction in the chip is triggered by an applied current or voltage then to happen an internal latching current. The high temperature generated by the internal latching current will burn the internal circuit or cause the circuit to work abnormally. This paper is to discuss when the IC happen latch-up, we need to prepare different test sample ex. "de-cap package sample front side sample" / "de-cap package sample back side COB (chip on board) sample"/ Blue tape COB backside sample. We also compare the difference between each test samples. Finally we discuss EMMI (Emission Microscope) hot spot experiment for latch-up simulation that needs limited of current with each different COB sample. The stress current limitation will induce EMMI result, based on this fail model and improve the product Latch-up performance by reducing parasitic BJT (bipolar transistor) circuit current gain factor ß.
{"title":"EMMI Abnormal Hotspot Study for Latch up Simulation","authors":"Huang Chia-Sheng, Guo Xuan-Chao, Chen Zhi-Wei, Lin shin-chia, Zhang Sheng-ru, Tsai Bo-an","doi":"10.1109/IPFA47161.2019.8984832","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984832","url":null,"abstract":"Latch-Up is a common circuit design problem in product reliability. Because of the poor design of the integrated circuit, the P-N-P-N junction in the chip is triggered by an applied current or voltage then to happen an internal latching current. The high temperature generated by the internal latching current will burn the internal circuit or cause the circuit to work abnormally. This paper is to discuss when the IC happen latch-up, we need to prepare different test sample ex. \"de-cap package sample front side sample\" / \"de-cap package sample back side COB (chip on board) sample\"/ Blue tape COB backside sample. We also compare the difference between each test samples. Finally we discuss EMMI (Emission Microscope) hot spot experiment for latch-up simulation that needs limited of current with each different COB sample. The stress current limitation will induce EMMI result, based on this fail model and improve the product Latch-up performance by reducing parasitic BJT (bipolar transistor) circuit current gain factor ß.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124947581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984901
Gregory M. Johnson, A. Rummel, M. Kemmler, T. Lundquist, Baohua Nui
Probing is increasingly utilized for characterization of local electrical properties of ICs, as well as for defect isolation. Test structures and/or SRAM arrays were examined with various probing modes, i.e. Electron Beam Induced Current (EBIC), both one and two probe Electron Beam Absorbed Current (EBAC), and EBIRCH (Electron Beam Induced Resistance CHange). The results demonstrate the value of using each for SRAM yield management. EBIC provides for imaging of depletion zones between p-wells and n-wells, even in a planar view. EBAC can provide information on basic connectivity as well as enabling isolation of resistive areas along a conductor. EBIRCH, being driven by two different mechanisms (thermal coefficient of resistivity and Seebeck effect) can provide two different analysis types, depending on conditions. EBIRCH not only precisely isolated the fin responsible for a short, but also highlighted the thermal relations between the elements of a pulldown device in an SRAM. These techniques together provide multiple forms of process feedback in an integrated yield management program involving analysis of via chains, SRAM parallel array test structures, and SRAMs.
{"title":"Probing SRAM Signals for Yield Management","authors":"Gregory M. Johnson, A. Rummel, M. Kemmler, T. Lundquist, Baohua Nui","doi":"10.1109/IPFA47161.2019.8984901","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984901","url":null,"abstract":"Probing is increasingly utilized for characterization of local electrical properties of ICs, as well as for defect isolation. Test structures and/or SRAM arrays were examined with various probing modes, i.e. Electron Beam Induced Current (EBIC), both one and two probe Electron Beam Absorbed Current (EBAC), and EBIRCH (Electron Beam Induced Resistance CHange). The results demonstrate the value of using each for SRAM yield management. EBIC provides for imaging of depletion zones between p-wells and n-wells, even in a planar view. EBAC can provide information on basic connectivity as well as enabling isolation of resistive areas along a conductor. EBIRCH, being driven by two different mechanisms (thermal coefficient of resistivity and Seebeck effect) can provide two different analysis types, depending on conditions. EBIRCH not only precisely isolated the fin responsible for a short, but also highlighted the thermal relations between the elements of a pulldown device in an SRAM. These techniques together provide multiple forms of process feedback in an integrated yield management program involving analysis of via chains, SRAM parallel array test structures, and SRAMs.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122496343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, it is confirmed that the electrostatic discharge is the cause of failure of the microwave module. The confirmation is based on a series of failure analysis, simulation tests as well as theoretical analysis on the failure case of a microwave module. In order to ensure the microwave performance, no electrostatic protection circuit was designed during the production and application of microwave modules, thus making the electrostatic discharge one of the main reasons for microwave module failure. In this paper, the characteristics of the harm of ESD toward microwave module are analyzed and an improved method is proposed through verification test. That is to add electrostatic protection measures around the circuit. This case provides reference and basis for prevention and control of electrostatic discharge hazards during production and application of microwave modules in the future.
{"title":"Failure Analysis of Microwave Module by ESD Effect","authors":"Zhimin Ding, Chao Duan, Xiaoqing Wang, Zhaoxi Wu, Yang Tian, Meng Meng","doi":"10.1109/IPFA47161.2019.8984833","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984833","url":null,"abstract":"In this paper, it is confirmed that the electrostatic discharge is the cause of failure of the microwave module. The confirmation is based on a series of failure analysis, simulation tests as well as theoretical analysis on the failure case of a microwave module. In order to ensure the microwave performance, no electrostatic protection circuit was designed during the production and application of microwave modules, thus making the electrostatic discharge one of the main reasons for microwave module failure. In this paper, the characteristics of the harm of ESD toward microwave module are analyzed and an improved method is proposed through verification test. That is to add electrostatic protection measures around the circuit. This case provides reference and basis for prevention and control of electrostatic discharge hazards during production and application of microwave modules in the future.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"210 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122626076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984893
Xiaotong Ma, Meng Zhang, Zhendong Jiang, Sunbin Deng, Yan Yan, Guijun Li, Rongsheng Chen, M. Wong, H. Kwok
Output breakdown (OBD) characteristics of metal oxide thin film transistors (TFTs) is studied. Three kinds of OBD behaviors are observed, corresponding to off state, subthreshold region and on state. The device degradation behaviors under OBD voltage stress is investigated. OBD stress can induce severe device degradation in very short stress time. The degradation mechanism is tentatively discussed, incorporated with TCAD simulation.
{"title":"Output Breakdown Characteristics and the Related Degradation Behaviors in Metal Oxide Thin Film Transistors","authors":"Xiaotong Ma, Meng Zhang, Zhendong Jiang, Sunbin Deng, Yan Yan, Guijun Li, Rongsheng Chen, M. Wong, H. Kwok","doi":"10.1109/IPFA47161.2019.8984893","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984893","url":null,"abstract":"Output breakdown (OBD) characteristics of metal oxide thin film transistors (TFTs) is studied. Three kinds of OBD behaviors are observed, corresponding to off state, subthreshold region and on state. The device degradation behaviors under OBD voltage stress is investigated. OBD stress can induce severe device degradation in very short stress time. The degradation mechanism is tentatively discussed, incorporated with TCAD simulation.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128494356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Image compressor in aerospace application is susceptible to single event effect, causing encoder logic errors and system errors. Therefore, the image compressor in aerospace application must be specially designed to improve the reliability of image information. Compression efficiency of JPEG-LS is higher than JPEG2000 and compression effect is better than lossless JPEG. Especially, JPEG-LS algorithm has the characteristics of low complexity and easy hardware implementation, which will save hardware resources of spaceborne system. An image compressor based on lossless JPEG-LS algorithm is designed in this paper, which can correctly compress 512×512 8-bit wide grayscale images. It is hardened by three-mode redundancy, Hamming code, timeout detection, one-hot code, and inter-process independently. The results point out that the error rate caused by SEU is significantly reduced 19.48% using the hardened compressor in this paper.
{"title":"Design of Radiation-Hardened Image Compressor Based on Lossless JPEG-LS","authors":"Chunhua Qi, Jianning Ma, Mingxue Huo, Tianqi Wang, Guoliang Ma, Chaoming Liu, Yinghun Piao, Kairui Guo, Yanqing Zhang","doi":"10.1109/IPFA47161.2019.8984811","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984811","url":null,"abstract":"Image compressor in aerospace application is susceptible to single event effect, causing encoder logic errors and system errors. Therefore, the image compressor in aerospace application must be specially designed to improve the reliability of image information. Compression efficiency of JPEG-LS is higher than JPEG2000 and compression effect is better than lossless JPEG. Especially, JPEG-LS algorithm has the characteristics of low complexity and easy hardware implementation, which will save hardware resources of spaceborne system. An image compressor based on lossless JPEG-LS algorithm is designed in this paper, which can correctly compress 512×512 8-bit wide grayscale images. It is hardened by three-mode redundancy, Hamming code, timeout detection, one-hot code, and inter-process independently. The results point out that the error rate caused by SEU is significantly reduced 19.48% using the hardened compressor in this paper.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129012940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984799
Y. Illarionov, T. Grasser
The rich and fascinating properties of two-dimensional (2D) materials have recently inspired various intriguing ideas for post-silicon nanoelectronics. One of the most far reaching of them is the possible substitution of Si with 2D materials in modern field-effect transistors (FETs). Ideally, this should suppress short-channel effects and thus extend Moore’s law below 5nm channel lengths, while maintaining and possibly even overcoming the high performance of commercial Si devices. However, despite recent progress at fabricating 2D FETs, there is still no commercially competitive transistor technology. One of the main reasons for this is the relatively poor reliability of typical 2D FET prototypes, which suffer from hysteresis and bias-temperature instabilities (BTI) of the transistor characteristics. Despite this, the attention paid to this serious problem is impermissibly low. Here we discuss the main achievements at understanding the reliability of various 2D FETs, from the first prototypes to recently reported scalable devices.
{"title":"Reliability of 2D Field-Effect Transistors: from First Prototypes to Scalable Devices","authors":"Y. Illarionov, T. Grasser","doi":"10.1109/IPFA47161.2019.8984799","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984799","url":null,"abstract":"The rich and fascinating properties of two-dimensional (2D) materials have recently inspired various intriguing ideas for post-silicon nanoelectronics. One of the most far reaching of them is the possible substitution of Si with 2D materials in modern field-effect transistors (FETs). Ideally, this should suppress short-channel effects and thus extend Moore’s law below 5nm channel lengths, while maintaining and possibly even overcoming the high performance of commercial Si devices. However, despite recent progress at fabricating 2D FETs, there is still no commercially competitive transistor technology. One of the main reasons for this is the relatively poor reliability of typical 2D FET prototypes, which suffer from hysteresis and bias-temperature instabilities (BTI) of the transistor characteristics. Despite this, the attention paid to this serious problem is impermissibly low. Here we discuss the main achievements at understanding the reliability of various 2D FETs, from the first prototypes to recently reported scalable devices.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123358322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984755
Ooi Yong Khai, Jack Ng Yi Jie
Lock-in thermography (LIT) is a commonly used FA technique to perform fault isolation for parametric short failures in microelectronic devices as compared with Optical Beam Induced Resistance Change (OBIRCH). This is because the OBIRCH technique becomes significantly less sensitive for direct hard short circuit parametric failure. This paper presents a simple yet innovative and effective methodology to increase resistance variances during OBIRCH analysis in hard short failures to improve the fault isolation success rate.
{"title":"Innovative Methodology for Short Circuit Failure Localization by OBIRCH Analysis","authors":"Ooi Yong Khai, Jack Ng Yi Jie","doi":"10.1109/IPFA47161.2019.8984755","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984755","url":null,"abstract":"Lock-in thermography (LIT) is a commonly used FA technique to perform fault isolation for parametric short failures in microelectronic devices as compared with Optical Beam Induced Resistance Change (OBIRCH). This is because the OBIRCH technique becomes significantly less sensitive for direct hard short circuit parametric failure. This paper presents a simple yet innovative and effective methodology to increase resistance variances during OBIRCH analysis in hard short failures to improve the fault isolation success rate.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121492911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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