Isolation techniques for 256 Mbit SOI DRAM application

Abstract

Various isolation techniques on SOI wafer were examined for the 256 Mbit DRAM application. The LOCOS technique results in good isolation down to 0.6 /spl mu/m pitch, in terms of encroachment and subthreshold characteristics. The encroachment of SOI wafers is slightly better than that of bulk wafers on the thick SOI wafers and expect to be even better on the thin SOI wafers. It is the most efficient way to adopt LOCOS isolation for the 256 Mbit SOI DRAM because of many years of process development experience in the bulk technology. In addition, the LOCOS isolation provides no edge leakage to the devices on SOI wafers. However, the LOCOS isolation technique may be limited as the DRAM cell pitch continue to scale down. The MESA isolation provides encroachment free for all ranges of SOI thickness. However, the MESA isolation morphology varies with the size of the isolation region. This could introduce edge leakage in devices with wide isolation region. The morphology variation can be solved with Chemical Mechanical Polishing (CMP) technology and it is expected not to be an issue in the near future. The edge leakage can be suppressed by angled channel stop implant and with mesa corner rounding treatment. As the DRAM cell pitch continue to scale down, the MESA isolation technique may be the only candidate for the 1 Gbit and beyond SOI DRAM.