P. Galy, J. Bourgeat, J. Jimenez, C. Entringer, A. Dray, B. Jacquier
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引用次数: 9
Abstract
The Electrostatic Discharge (ESD) protection for advanced CMOS technologies is a challenge due to the technology scaling down. The main purpose of this paper is to present and compare silicon results in C45nm CMOS technology of a single pitch ESD protection using isolated Silicon Controlled Rectifier (SCR) and dual isolated SCR. These two protection structures with dynamic trigger circuit will be compared. Also, the power pad clamps in 1 pitch IO are qualified through 100ns TLP. Silicon result show that ESD robustness reaches 4kV HBM, 200V MM and 500V CDM for a 64 BGA package. IO power pads are also immune to Latch Up and power sequence.
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