Wafer bonding for intelligent power ICs: integration of vertical structures

Abstract

Intelligent power ICs are increasingly desired for applications in automotive electronics, motor control devices or flat panel displays. In order to meet the requirements regarding reliability, low area consumption and flexibility the dielectric isolation is superior to the other isolation techniques such as self isolation or junction isolation. Integrated power devices on fully isolated SOI wafers showed the advantages of bonded SOI material for this application. However, the full isolation restricts the power devices to area consuming lateral devices or up-drain DMOS type devices only suitable for medium power applications. Devices with high current and high breakdown voltage capability require vertical transistor types. So far, different attempts have been made to integrate vertical connected and dielectrically isolated areas on one wafer. We have developed a process, which allows the fabrication of vertical connected areas and device isolation before bonding and requires no special alignment. First, the area for the vertical contact is patterned and covered with a silicon nitride layer. Subsequently, V-grooves are patterned, etched and thermally oxidised. After removal of the nitride layer the V-grooves are filled with polysilicon. Depending on the deposition conditions, the vertical contact area is filled with polysilicon or epitaxial grown silicon. Thinning occurs by chemo-mechanical polishing. As in the "classical" DI process the oxide at the bottom of the V-groove serves as a polishing stop resulting in a better SOI thickness uniformity.