{"title":"Parasitic conscious 54 GHz divide-by-4 injection-locked frequency divider","authors":"K. Katayama, S. Amakawa, K. Takano, M. Fujishima","doi":"10.1109/RFIT.2015.7377901","DOIUrl":null,"url":null,"abstract":"An injection-locked frequency divider (ILFD) is utilized to divide the frequency of a voltage-controlled oscillator (VCO). We propose an ILFD that can be directly connected to a VCO by minimizing the input capacitance of the input nodes. The capacitance is reduced by limiting the number of MOSFETs connected to the injection nodes. We fabricated a 54 GHz divide-by-4 ILFD using 65 nm CMOS technology whose core area is 60 × 90 μm2. By limiting the number of driven MOSFETs and reducing the parasitic capacitance, a locking range of 430 MHz is achieved at a -20 dBm input. The power consumption is 21 mW with a 1.2 V supply and the phase noise is -120 dBc/Hz at a 1 MHz offset.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIT.2015.7377901","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
An injection-locked frequency divider (ILFD) is utilized to divide the frequency of a voltage-controlled oscillator (VCO). We propose an ILFD that can be directly connected to a VCO by minimizing the input capacitance of the input nodes. The capacitance is reduced by limiting the number of MOSFETs connected to the injection nodes. We fabricated a 54 GHz divide-by-4 ILFD using 65 nm CMOS technology whose core area is 60 × 90 μm2. By limiting the number of driven MOSFETs and reducing the parasitic capacitance, a locking range of 430 MHz is achieved at a -20 dBm input. The power consumption is 21 mW with a 1.2 V supply and the phase noise is -120 dBc/Hz at a 1 MHz offset.