On the testability of realistic bridging faults

Abstract

Discusses the preliminary simulation results concerning the coverage of realistic bridging faults, according to an experimental fault classification of node shorts between logic nodes. There is evidence to support that, prior to simulation, difficult to detect faults can be identified, according to their topological characteristics. This may allow the definition of manageable subsets of bridging faults, whose avoidance by layout reconfiguration may be rewarding.<>