Chip-packaging interaction in Cu/very low-k interconnect

Abstract

Chip-Package interaction (CPI) has drawn much attention for very low-k (VLK) packaging technology development, especially as the electronic industry is moving from SnPb solder to lead-free solder. In this study, a multi-level finite element model is used to optimize the interconnect scheme from a packaging reliability point of view. Factors including top metal (or SiO2) thickness, passivation dielectric layers, and bump pad structure are found to play key roles in packaging process and reliability.