Pub Date : 2009-06-01DOI: 10.1109/IITC.2009.5090347
M. Lin, N. Jou, James W. Liang, A. Juan, K. Su
Upstream Electromigration (EM) study was performed on different multiple via structures with different Cu line dimensions. EM performance was found to be dependent on both via layout and Cu line dimension. Failure analysis showed different EM failure modes and diffusion paths on these structures with their different grain morphology. Finite element analysis is applied to find out the current density profiles of these structures and explain their EM results. Simulated resistance increase was found to be dependent on the size and location of EM induced void in these structures.
{"title":"Upstream electromigration study on multiple via structures in copper interconnect","authors":"M. Lin, N. Jou, James W. Liang, A. Juan, K. Su","doi":"10.1109/IITC.2009.5090347","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090347","url":null,"abstract":"Upstream Electromigration (EM) study was performed on different multiple via structures with different Cu line dimensions. EM performance was found to be dependent on both via layout and Cu line dimension. Failure analysis showed different EM failure modes and diffusion paths on these structures with their different grain morphology. Finite element analysis is applied to find out the current density profiles of these structures and explain their EM results. Simulated resistance increase was found to be dependent on the size and location of EM induced void in these structures.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"15 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123268765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-06-01DOI: 10.1109/IITC.2009.5090362
Steve Wang, J. Gelb, S. H. Lau, W. Yun
Metrology of 3D integrated circuits (IC) have presented new challenges to existing metrology technologies, particularly in cases where the 3D structure of the sample must be measured non-destructively. X-ray microscopy, on the other hand, offers very deep penetration and better than 50 nm resolution, as well as ability to distinguish different elemental compositions. When combined with computed tomography (CT) technology, the full 3D structure of an IC an be obtained non-destructively at tens of nanometer accuracy, thus making x-ray nano-CT well suited for both metrology and failure analysis (FA) applications with 3D IC.
{"title":"Metrology of 3D IC with X-ray Microscopy and nano-scale X-ray CT","authors":"Steve Wang, J. Gelb, S. H. Lau, W. Yun","doi":"10.1109/IITC.2009.5090362","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090362","url":null,"abstract":"Metrology of 3D integrated circuits (IC) have presented new challenges to existing metrology technologies, particularly in cases where the 3D structure of the sample must be measured non-destructively. X-ray microscopy, on the other hand, offers very deep penetration and better than 50 nm resolution, as well as ability to distinguish different elemental compositions. When combined with computed tomography (CT) technology, the full 3D structure of an IC an be obtained non-destructively at tens of nanometer accuracy, thus making x-ray nano-CT well suited for both metrology and failure analysis (FA) applications with 3D IC.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116023869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-06-01DOI: 10.1109/IITC.2009.5090396
G. Lopez, J. Davis, J. Meindl
A new closed-form effective resistivity (rhoeff) model as a function of line-edge roughness (LER), sidewall specularity p, and grain boundary scattering R is presented. There is improved physical insight to increasing resistivity than previous models. The model is validated against former simulation data and calibrated with electrical measurements of fabricated Cu interconnect test structures exhibiting an average of 14 nm LER for line widths ranging from 61 nm to 332 nm. Upon fitting the new model to experimental data, p and R are determined to be 0 and 0.79, respectively. The model is also used to interpret ITRS 2007 projections for local wire resistivity. ITRS projections for resistivity can only be achieved with very high quality interconnect structures that have nearly elastic sidewall collisions (p=0.95), low grain reflectivity (R=0.40), and no line edge roughness (LER=0nm). In fact, adding 6.0nm of LER increases rhoeff by ~20% for 2022 (11nm node). Finally, a projection with pessimistic values of p=0, R=0.5 and LER=1.0nm predicts an 87% greater rhoeff value than the ITRS 2007 projection for the 11 nm node.
{"title":"A new physical model and experimental measurements of copper interconnect resistivity considering size effects and line-edge roughness (LER)","authors":"G. Lopez, J. Davis, J. Meindl","doi":"10.1109/IITC.2009.5090396","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090396","url":null,"abstract":"A new closed-form effective resistivity (rhoeff) model as a function of line-edge roughness (LER), sidewall specularity p, and grain boundary scattering R is presented. There is improved physical insight to increasing resistivity than previous models. The model is validated against former simulation data and calibrated with electrical measurements of fabricated Cu interconnect test structures exhibiting an average of 14 nm LER for line widths ranging from 61 nm to 332 nm. Upon fitting the new model to experimental data, p and R are determined to be 0 and 0.79, respectively. The model is also used to interpret ITRS 2007 projections for local wire resistivity. ITRS projections for resistivity can only be achieved with very high quality interconnect structures that have nearly elastic sidewall collisions (p=0.95), low grain reflectivity (R=0.40), and no line edge roughness (LER=0nm). In fact, adding 6.0nm of LER increases rhoeff by ~20% for 2022 (11nm node). Finally, a projection with pessimistic values of p=0, R=0.5 and LER=1.0nm predicts an 87% greater rhoeff value than the ITRS 2007 projection for the 11 nm node.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"292 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117329053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-06-01DOI: 10.1109/IITC.2009.5090363
A. Urbanowicz, V. V. Talanov, Marianna Pantouvaki, Herbert Struyf, S. Gendt, M. R. Baklanov
The effect of ash chemistry on dielectric constant of blanket and patterned low-k was studied using a near-field scanning probe microwave microscope, known commercially as NeoMetriK™ technology. Two common photoresist ash approaches with the same etch sequence were studied: plasma assisted sublimation of photoresist at elevated temperature and ion-assisted ash at room temperature. The results for blanket low-k agree well with the FTIR and water source ellipsometric porosimetry (WEP) measurements. The amount of sidewall damage measured in patterned structures before metallization confirms the expected trends.
{"title":"Evaluation of plasma damage in blanket and patterned low-k structures by near-field scanning probe microwave microscope: effect of plasma ash chemistry","authors":"A. Urbanowicz, V. V. Talanov, Marianna Pantouvaki, Herbert Struyf, S. Gendt, M. R. Baklanov","doi":"10.1109/IITC.2009.5090363","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090363","url":null,"abstract":"The effect of ash chemistry on dielectric constant of blanket and patterned low-k was studied using a near-field scanning probe microwave microscope, known commercially as NeoMetriK™ technology. Two common photoresist ash approaches with the same etch sequence were studied: plasma assisted sublimation of photoresist at elevated temperature and ion-assisted ash at room temperature. The results for blanket low-k agree well with the FTIR and water source ellipsometric porosimetry (WEP) measurements. The amount of sidewall damage measured in patterned structures before metallization confirms the expected trends.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"11 15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121558091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-06-01DOI: 10.1109/IITC.2009.5090337
K. Takayanagi, Y. Oshima, Y. Kurui
Electron transport in gold nanowires is studied by transmission electron microscopy (TEM) simultaneously with conductance measurement by using a scanning tunneling tip as an electrode. Conductance evolution while thinning of a gold nanowire shows sequential steps until it breaks after forming a single atomic chain. The step heights coincide the quantum unit, G0 = 2e2/h = (12.9kΩ)−1, except a little deviation due to multiple reflection. Gold nanowires fabricated in the ≪110≫ orientation can elongate to a several nanometer in length, and show linear current—voltage relation even for the bias voltage of 0.2V. Gold nanowires, thus, behave as a ballistic conductor, and their conductance is quantized to carry current, 1µA per single atomic chain at the bias voltage of 13mV.
{"title":"Conductance quantization of gold nanowires as a ballistic conductor","authors":"K. Takayanagi, Y. Oshima, Y. Kurui","doi":"10.1109/IITC.2009.5090337","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090337","url":null,"abstract":"Electron transport in gold nanowires is studied by transmission electron microscopy (TEM) simultaneously with conductance measurement by using a scanning tunneling tip as an electrode. Conductance evolution while thinning of a gold nanowire shows sequential steps until it breaks after forming a single atomic chain. The step heights coincide the quantum unit, G0 = 2e2/h = (12.9kΩ)−1, except a little deviation due to multiple reflection. Gold nanowires fabricated in the ≪110≫ orientation can elongate to a several nanometer in length, and show linear current—voltage relation even for the bias voltage of 0.2V. Gold nanowires, thus, behave as a ballistic conductor, and their conductance is quantized to carry current, 1µA per single atomic chain at the bias voltage of 13mV.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134091647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-06-01DOI: 10.1109/IITC.2009.5090346
T. Oszinda, M. Schaller, D. Fischer, S. Schulz
The diffusion behavior of different solvents and repair chemicals in a porous SiCOH with pores of ∼ 1,5 nm was studied. It was found for molecule with a size ≤ 1/3 of the pore size the diffusion coefficient (De) depends mainly on the size of the molecule, while a size ≫ 1/3 of the pore size does not show a linear dependency of De on the molecules size. In this regime De is mainly a function of the surface diffusion which depends on the surface energies of the solid and the liquid and adsorption effects. This study show that the porosity and the surface energies influencing the diffusion need to study in order to perform satisfactory cleaning and repair process for ULK dielectric layers.
{"title":"Characterization of plasma damaged porous ULK SiCOH layers in aspect of changes in the diffusion behavior of solvents and repair-chemicals","authors":"T. Oszinda, M. Schaller, D. Fischer, S. Schulz","doi":"10.1109/IITC.2009.5090346","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090346","url":null,"abstract":"The diffusion behavior of different solvents and repair chemicals in a porous SiCOH with pores of ∼ 1,5 nm was studied. It was found for molecule with a size ≤ 1/3 of the pore size the diffusion coefficient (De) depends mainly on the size of the molecule, while a size ≫ 1/3 of the pore size does not show a linear dependency of De on the molecules size. In this regime De is mainly a function of the surface diffusion which depends on the surface energies of the solid and the liquid and adsorption effects. This study show that the porosity and the surface energies influencing the diffusion need to study in order to perform satisfactory cleaning and repair process for ULK dielectric layers.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117080786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-06-01DOI: 10.1109/IITC.2009.5090354
H. Kitada, N. Maeda, K. Fujimoto, K. Suzuki, A. Kawai, K. Arai, T. Suzuki, T. Nakamura, T. Ohba
In the trough silicon via (TSV) structure for 3-dimentional integration (3DI), large thermal-mechanical stress acts in the BEOL layer caused by the mismatch in thermal expansion coefficient (CTE) of the TSV materials. The resulting high-stress region is thought to be the critical point for the initiation of the cracking or the de-lamination that affects the mechanical reliability. In this study, the stress of multi-stacked thin Si wafers composed of copper TSV and copper/low-k BEOL structure was analyzed by the finite element method (FEM), aiming to reduce the stress of LSI devices of 3D-IC. The results of sensitivity analysis using design of experiment (DOE) indicated that the thickness of the adhesive layer is the key factor for the structural integration of TSV design. It is suggested that the wafer-on-a-wafer (WOW) process has reliability about 1.5 to 1.75 times higher in the TSV structure with BEOL interconnects.
{"title":"Stress sensitivity analysis on TSV structure of wafer-on-a-wafer (WOW) by the finite element method (FEM)","authors":"H. Kitada, N. Maeda, K. Fujimoto, K. Suzuki, A. Kawai, K. Arai, T. Suzuki, T. Nakamura, T. Ohba","doi":"10.1109/IITC.2009.5090354","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090354","url":null,"abstract":"In the trough silicon via (TSV) structure for 3-dimentional integration (3DI), large thermal-mechanical stress acts in the BEOL layer caused by the mismatch in thermal expansion coefficient (CTE) of the TSV materials. The resulting high-stress region is thought to be the critical point for the initiation of the cracking or the de-lamination that affects the mechanical reliability. In this study, the stress of multi-stacked thin Si wafers composed of copper TSV and copper/low-k BEOL structure was analyzed by the finite element method (FEM), aiming to reduce the stress of LSI devices of 3D-IC. The results of sensitivity analysis using design of experiment (DOE) indicated that the thickness of the adhesive layer is the key factor for the structural integration of TSV design. It is suggested that the wafer-on-a-wafer (WOW) process has reliability about 1.5 to 1.75 times higher in the TSV structure with BEOL interconnects.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128775728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-06-01DOI: 10.1109/IITC.2009.5090358
T. Yamazaki, M. Hirakawa, T. Nakayama, H. Murakami
Porous silica spin-on dielectrics (SOD) films with low dielectric constant (k ∼ 2.0), high Young's modulus (E ∼ 7.5 GPa), and small pores (∼ 0.2 nm) were obtained only with ultraviolet (UV) curing within 1min at 350 °C but without hydrophobic treatment process. Optimized UV curing condition and composition of precursor solution can give the low-k film applicable to 32 nm-node interconnect technology and beyond.
{"title":"Development of porous silica ultra low-k films for 32 nm-node interconnects and beyond","authors":"T. Yamazaki, M. Hirakawa, T. Nakayama, H. Murakami","doi":"10.1109/IITC.2009.5090358","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090358","url":null,"abstract":"Porous silica spin-on dielectrics (SOD) films with low dielectric constant (k ∼ 2.0), high Young's modulus (E ∼ 7.5 GPa), and small pores (∼ 0.2 nm) were obtained only with ultraviolet (UV) curing within 1min at 350 °C but without hydrophobic treatment process. Optimized UV curing condition and composition of precursor solution can give the low-k film applicable to 32 nm-node interconnect technology and beyond.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"31 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114033425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-06-01DOI: 10.1109/IITC.2009.5090400
R. Brain, S. Agrawal, D. Becher, R. Bigwood, M. Buehler, V. Chikarmane, M. Childs, J. Choi, Shannon E. Daviess, C. Ganpule, Jun He, P. Hentges, I. Jin, S. Klopcic, G. Malyavantham, B. McFadden, J. Neulinger, J. Neirynck, Y. Neirynck, C. Pelto, P. Plekhanov, Y. Shusterman, T. Van, Martin Weiss, S. Williams, F. Xia, P. Yashar, A. Yeoh
Interconnect process features are described for a 32nm high performance logic technology. Lower-k, yet highly manufacturable, Carbon-Doped Oxide (CDO) dielectric layers are introduced on this technology at three layers to address the demand for ever lower metal line capacitance. The pitches have been aggressively scaled to meet the expectation for density, and the metal resistance and electromigration performance have been carefully balanced to meet the high reliability requirements while maintaining the lowest possible resistance. A new patterning scheme has been used to limit any patterning damage to the lower-k ILD and address the increasingly difficult problem of via-to-metal shorting at these very tight pitches. The interconnect stack has a thick Metal-9 layer to provide a low resistance path for the power and I/O routing that has been carefully scaled to maintain a low resistance. The combined interconnect stack provides high density, performance, and reliability, and supports a Pb-free 32nm process.
{"title":"Low-k interconnect stack with a novel self-aligned via patterning process for 32nm high volume manufacturing","authors":"R. Brain, S. Agrawal, D. Becher, R. Bigwood, M. Buehler, V. Chikarmane, M. Childs, J. Choi, Shannon E. Daviess, C. Ganpule, Jun He, P. Hentges, I. Jin, S. Klopcic, G. Malyavantham, B. McFadden, J. Neulinger, J. Neirynck, Y. Neirynck, C. Pelto, P. Plekhanov, Y. Shusterman, T. Van, Martin Weiss, S. Williams, F. Xia, P. Yashar, A. Yeoh","doi":"10.1109/IITC.2009.5090400","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090400","url":null,"abstract":"Interconnect process features are described for a 32nm high performance logic technology. Lower-k, yet highly manufacturable, Carbon-Doped Oxide (CDO) dielectric layers are introduced on this technology at three layers to address the demand for ever lower metal line capacitance. The pitches have been aggressively scaled to meet the expectation for density, and the metal resistance and electromigration performance have been carefully balanced to meet the high reliability requirements while maintaining the lowest possible resistance. A new patterning scheme has been used to limit any patterning damage to the lower-k ILD and address the increasingly difficult problem of via-to-metal shorting at these very tight pitches. The interconnect stack has a thick Metal-9 layer to provide a low resistance path for the power and I/O routing that has been carefully scaled to maintain a low resistance. The combined interconnect stack provides high density, performance, and reliability, and supports a Pb-free 32nm process.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127756469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-06-01DOI: 10.1109/IITC.2009.5090329
T. Bao, H. Chen, C.J. Lee, H. Lu, H.W. Chen, H. Tsai, C.C. Lin, S. Jeng, S. Shue, C. Yu
Challenges of various Low Effective-K approaches, including homogeneous Low-K and Air-Gap, for next generation Cu/Low-K interconnect will be presented. For homogeneous Low-K approach, top issues and possible solutions for K damage, package, and CMP peeling & plannarization due to introduction of fragile lower k (K≪2.4) insulator will be focused. For Air-Gap, various types of Air-Gaps will be reviewed from the points of cost, layout/designer, and new processes involved.
{"title":"Challenges of Low Effective-K approaches for future Cu interconnect","authors":"T. Bao, H. Chen, C.J. Lee, H. Lu, H.W. Chen, H. Tsai, C.C. Lin, S. Jeng, S. Shue, C. Yu","doi":"10.1109/IITC.2009.5090329","DOIUrl":"https://doi.org/10.1109/IITC.2009.5090329","url":null,"abstract":"Challenges of various Low Effective-K approaches, including homogeneous Low-K and Air-Gap, for next generation Cu/Low-K interconnect will be presented. For homogeneous Low-K approach, top issues and possible solutions for K damage, package, and CMP peeling & plannarization due to introduction of fragile lower k (K≪2.4) insulator will be focused. For Air-Gap, various types of Air-Gaps will be reviewed from the points of cost, layout/designer, and new processes involved.","PeriodicalId":301012,"journal":{"name":"2009 IEEE International Interconnect Technology Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128040632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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