RAAPS: Reliability Aware ArchC based Processor Simulator

Abstract

In semiconductor industry, designing a SoC is a complex process. Designing reliable SoCs includes study of various configurations involving different operating conditions and considering both hard and soft errors. Designers at higher level of abstraction already have many ways to remove or handle soft errors. This paper aims at analyzing hard errors at functional level. We propose a methodology using state of the art failure models and simulators to provide the cumulative failure rate for a processor simulated at functional level.