A new manufacturing method of CMOS logic compatible 1T-CRRAM

Abstract

This study proposed a new manufacturing method for improving the fabrication yield of CRRAM in advanced 90nm CMOS logic process. The original CMOS compatible CRRAM is proposed to fabricate by the thickness and size control of contact etch process. Due to the variation of contact hole etch on different ILD topographies, the remained RRAM's TMO could result in uniformity and yield problems of memory arrays. In order to decline the production variation, a new refilling Contact RRAM process is firstly proposed and demonstrated in this paper.