Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480492
A. Afzalian, M. Passlack, Y. Yeo
Atomistic device simulations are presented to assess the potential of InAs/GaSb GAA NW n- and p-TFETs with diameter d of 5.45 nm. Using a recent breakthrough in atomistic modeling, more than 100× reduction in simulation time was achieved using a tight binding mode-space approach. This enabled full-band transport simulation for a device with ~100,000 atoms, employing an accurate sp3s*SO (10 orbitals/atom) tight binding basis. At IOFF of 10 pA/μm, an optimized n-TFET with a pocket region is predicted to have ION of 46 and 196 μA/μm at VDD of 0.3, and 0.5 V, respectively. This achieves a better energy-delay product than its MOSFET counterpart. Through careful design, similar performance can be achieved for p- and n- TFETs.
{"title":"Atomistic simulation of gate-all-around GaSb/InAs nanowire TFETs using a fast full-band mode-space NEGF model","authors":"A. Afzalian, M. Passlack, Y. Yeo","doi":"10.1109/VLSI-TSA.2016.7480492","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480492","url":null,"abstract":"Atomistic device simulations are presented to assess the potential of InAs/GaSb GAA NW n- and p-TFETs with diameter d of 5.45 nm. Using a recent breakthrough in atomistic modeling, more than 100× reduction in simulation time was achieved using a tight binding mode-space approach. This enabled full-band transport simulation for a device with ~100,000 atoms, employing an accurate sp3s*SO (10 orbitals/atom) tight binding basis. At IOFF of 10 pA/μm, an optimized n-TFET with a pocket region is predicted to have ION of 46 and 196 μA/μm at VDD of 0.3, and 0.5 V, respectively. This achieves a better energy-delay product than its MOSFET counterpart. Through careful design, similar performance can be achieved for p- and n- TFETs.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124815455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480504
F. Boeuf, Kirk Ouellette
Recently Silicon Photonics received a lot of interest due to the increased need of high-data rate and low-cost transceivers in datacenters, mainly driven by cloud applications. In this paper we will demonstrate the industrialization of Si-Photonics in a CMOS fab addressing the datacenter market and more particularly the 100Gbits/s PSM-4 standard operating at 1310nm wavelength.
{"title":"Industrialization of Si-Photonics into a 300mm CMOS fab","authors":"F. Boeuf, Kirk Ouellette","doi":"10.1109/VLSI-TSA.2016.7480504","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480504","url":null,"abstract":"Recently Silicon Photonics received a lot of interest due to the increased need of high-data rate and low-cost transceivers in datacenters, mainly driven by cloud applications. In this paper we will demonstrate the industrialization of Si-Photonics in a CMOS fab addressing the datacenter market and more particularly the 100Gbits/s PSM-4 standard operating at 1310nm wavelength.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125905128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480499
Kibong Moon, E. Cha, Daeseok Lee, Junwoo Jang, Jaesung Park, H. Hwang
We report nanoscale oxide based analog synpase device and Insulator-Metal-Transition (IMT) oscillator neuron device for neuromorphic system [1,2]. By controlling the redox reaction at Metal/Pr0.7Ca0.3MnO3 (PCMO) interface, we can control synapse characteristics such as switching uniformity, disturbance, retention and multi-level data storage under identical pulse condition. Among various metal electrodes, we found that Mo electrode shows the best data retention characteristics. Using IMT characteristics of NbO2 film, we developed IMT oscillator for neuron application. We have experimentally confirmed the realization of pattern recognition with high accuracy using the Mo/PCMO synapse array and NbO2 oscillator neuron.
{"title":"ReRAM-based analog synapse and IMT neuron device for neuromorphic system","authors":"Kibong Moon, E. Cha, Daeseok Lee, Junwoo Jang, Jaesung Park, H. Hwang","doi":"10.1109/VLSI-TSA.2016.7480499","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480499","url":null,"abstract":"We report nanoscale oxide based analog synpase device and Insulator-Metal-Transition (IMT) oscillator neuron device for neuromorphic system [1,2]. By controlling the redox reaction at Metal/Pr0.7Ca0.3MnO3 (PCMO) interface, we can control synapse characteristics such as switching uniformity, disturbance, retention and multi-level data storage under identical pulse condition. Among various metal electrodes, we found that Mo electrode shows the best data retention characteristics. Using IMT characteristics of NbO2 film, we developed IMT oscillator for neuron application. We have experimentally confirmed the realization of pattern recognition with high accuracy using the Mo/PCMO synapse array and NbO2 oscillator neuron.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"41 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123728257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480488
Jhih-Yang Yan, Sun-Rong Jan, Yi-Chung Huang, H. Lan, C. W. Liu, Y.-H. Huang, B. Hung, K.T. Chan, Michael Huang, M. Yang
Impact of via-last through-silicon via (TSV) on 28nm node devices is investigated. The stress field of TSV is affected by the back-end-of-line (BEOL) dielectrics. The absolute value of radial stress (|σr|) is different from that of tangential stress (|σθ|) on silicon, which leads to the asymmetric keep-out zone (KOZ). The physics behind the asymmetry is also described. A modified KOZ model considering the asymmetric stress field is proposed and verified by experiment data.
{"title":"Compact modeling and simulation of TSV with experimental verification","authors":"Jhih-Yang Yan, Sun-Rong Jan, Yi-Chung Huang, H. Lan, C. W. Liu, Y.-H. Huang, B. Hung, K.T. Chan, Michael Huang, M. Yang","doi":"10.1109/VLSI-TSA.2016.7480488","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480488","url":null,"abstract":"Impact of via-last through-silicon via (TSV) on 28nm node devices is investigated. The stress field of TSV is affected by the back-end-of-line (BEOL) dielectrics. The absolute value of radial stress (|σr|) is different from that of tangential stress (|σθ|) on silicon, which leads to the asymmetric keep-out zone (KOZ). The physics behind the asymmetry is also described. A modified KOZ model considering the asymmetric stress field is proposed and verified by experiment data.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"12 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117008844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480537
C. Carmignani, O. Rozeau, P. Scheiblin, A. Thuaire, P. Reynaud, S. Barraud, T. Ernst, S. Chéramy, M. Vinet
This paper proposes an extensive analysis of the impact of both structural effect and charge parameters on silicon nanowire-based biological sensors, for single-charge detection. These parameters are calibrated on physical and electrical characterizations and are subsequently introduced in a compact model to predict the signal over noise ratio (SNR). We finally propose rules for the design of nanowires and recommendations for the placement of the biological element, inducing the single charge release.
{"title":"Fine charge sensing using a silicon nanowire for biodetection","authors":"C. Carmignani, O. Rozeau, P. Scheiblin, A. Thuaire, P. Reynaud, S. Barraud, T. Ernst, S. Chéramy, M. Vinet","doi":"10.1109/VLSI-TSA.2016.7480537","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480537","url":null,"abstract":"This paper proposes an extensive analysis of the impact of both structural effect and charge parameters on silicon nanowire-based biological sensors, for single-charge detection. These parameters are calibrated on physical and electrical characterizations and are subsequently introduced in a compact model to predict the signal over noise ratio (SNR). We finally propose rules for the design of nanowires and recommendations for the placement of the biological element, inducing the single charge release.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124026058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480497
Ying‐Chen Chen, Yao‐Feng Chang, B. Fowler, F. Zhou, Xiaohan Wu, C. Hsieh, H. Chang, Chih-Hung Pan, Min-Chen Chen, Kuan‐Chang Chang, T. Tsai, T. Chang, Jack C. Lee
Intrinsic unipolar SiOx-based Resistive-RAM (ReRAM) characteristics have been investigated. The cross-bar MIM structures have been examined under AC frequency response, by varying device area, temperature and current states. The results provide additional insights into the hopping/switching mechanisms. For the first time, by using SiOx/HfOx stacking engineering, we have developed a low-voltage operation (<; 2V) for SiOx-based ReRAM. The SiOx/HfOx stacking optimization not only maintains the RS behaviors even in air environment without any programming window degradation, but also further reduces the switching voltage below 2V.
{"title":"Comprehensive study of intrinsic unipolar SiOx-based ReRAM characteristics in AC frequency response and low voltage (< 2V) operation","authors":"Ying‐Chen Chen, Yao‐Feng Chang, B. Fowler, F. Zhou, Xiaohan Wu, C. Hsieh, H. Chang, Chih-Hung Pan, Min-Chen Chen, Kuan‐Chang Chang, T. Tsai, T. Chang, Jack C. Lee","doi":"10.1109/VLSI-TSA.2016.7480497","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480497","url":null,"abstract":"Intrinsic unipolar SiOx-based Resistive-RAM (ReRAM) characteristics have been investigated. The cross-bar MIM structures have been examined under AC frequency response, by varying device area, temperature and current states. The results provide additional insights into the hopping/switching mechanisms. For the first time, by using SiOx/HfOx stacking engineering, we have developed a low-voltage operation (<; 2V) for SiOx-based ReRAM. The SiOx/HfOx stacking optimization not only maintains the RS behaviors even in air environment without any programming window degradation, but also further reduces the switching voltage below 2V.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129802279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-DAT.2016.7482589
Y. Papananos, Nikolaos Alexiou, Konstantinos Galanopoulos, David Seebacher, F. Dielacher
This paper presents a mixed-signal outphasing RF-PWM modulator with improved time resolution and high dynamic range realized in 40nm CMOS. Phase shifting is implemented using synchronously tapped analog delay lines comprising integrated L and C devices and achieving a fine-step delay of 2 ps while occupying acceptable silicon area and consuming zero power. The analog outputs of the delay lines are converted to CMOS-compatible square pulses that drive an AND gate which generates RF-PWM pulses with minimum pulse width of 10ps on a 50-Ohm load. According to system-integrated modulator co-simulation results, an ACLR of -45dBc is achieved from a 40 MHz baseband signal on a 2.65 GHz carrier.
{"title":"Mixed analog-digital pulse-width modulator for massive-MIMO transmitters","authors":"Y. Papananos, Nikolaos Alexiou, Konstantinos Galanopoulos, David Seebacher, F. Dielacher","doi":"10.1109/VLSI-DAT.2016.7482589","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2016.7482589","url":null,"abstract":"This paper presents a mixed-signal outphasing RF-PWM modulator with improved time resolution and high dynamic range realized in 40nm CMOS. Phase shifting is implemented using synchronously tapped analog delay lines comprising integrated L and C devices and achieving a fine-step delay of 2 ps while occupying acceptable silicon area and consuming zero power. The analog outputs of the delay lines are converted to CMOS-compatible square pulses that drive an AND gate which generates RF-PWM pulses with minimum pulse width of 10ps on a 50-Ohm load. According to system-integrated modulator co-simulation results, an ACLR of -45dBc is achieved from a 40 MHz baseband signal on a 2.65 GHz carrier.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122945422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480501
Yu-Hsuan Lin, Jau-Yi Wu, Ming-Hsiu Lee, Tien-Yen Wang, Yu-Yu Lin, F. Lee, Dai-Ying Lee, E. Lai, K. Chiang, H. Lung, K. Hsieh, T. Tseng, Chih-Yuan Lu
TMO ReRAMs, being built on defect states, are intrinsically subject to variability. In this work, cell to cell variability is studied by applying write shots with different current and voltage for Forming, SET and RESET operation, respectively. We found the keys to eliminate tail bits consist of (1) longer write pulse, (2) higher write current and (3) higher write voltage. In order to optimize the performance of write speed, write power and device reliability, we developed a novel resistance control method using a smart writing algorithm. Compared to the conventional ISPP writing scheme, this smart writing algorithm covers much wider switching condition variability and cell-to-cell variation by controlling both current and voltage for ReRAM operation.
{"title":"Excellent resistance variability control of WOx ReRAM by a smart writing algorithm","authors":"Yu-Hsuan Lin, Jau-Yi Wu, Ming-Hsiu Lee, Tien-Yen Wang, Yu-Yu Lin, F. Lee, Dai-Ying Lee, E. Lai, K. Chiang, H. Lung, K. Hsieh, T. Tseng, Chih-Yuan Lu","doi":"10.1109/VLSI-TSA.2016.7480501","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480501","url":null,"abstract":"TMO ReRAMs, being built on defect states, are intrinsically subject to variability. In this work, cell to cell variability is studied by applying write shots with different current and voltage for Forming, SET and RESET operation, respectively. We found the keys to eliminate tail bits consist of (1) longer write pulse, (2) higher write current and (3) higher write voltage. In order to optimize the performance of write speed, write power and device reliability, we developed a novel resistance control method using a smart writing algorithm. Compared to the conventional ISPP writing scheme, this smart writing algorithm covers much wider switching condition variability and cell-to-cell variation by controlling both current and voltage for ReRAM operation.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"171 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121165115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480515
V. Hu, Chang-Ting Lo, A. Sachid, P. Su, C. Hu
Corner spacer design is investigated to improve the performance of multi-gate InGaAs-OI FinFET with gate-to-source/drain underlap compared with the all vacuum and all nitride spacer devices. All vacuum spacer devices with low permittivity reduce fringing capacitance and improve performance. However, for gate-to-source/drain underlap InGaAs-OI FinFET, all vacuum spacer device degrades source/drain resistance (Rsd) and ON current (Ion), thus exhibiting slight improvement in inverter delay compared with the all nitride spacer device. Corner spacer design comprising of high-k and low-k composite spacer is proposed to optimize Rsd and capacitance, and hence improve delay. Various lengths and heights of corner spacer for InGaAs-OI FinFET with different underlap length and fin height aspect ratio are investigated to optimized performance. The optimized corner spacer design is: (a) the length of corner spacer (Lcorner) is approximately equal to underlap length (Lun), and (b) the height of corner spacer (Hcorner) is proportional to the sum of fin height (Hfin) and gate oxide thickness (Tox). Compared with the all vacuum spacer InGaAs-OI FinFET with Lun = 6 nm, the optimized corner spacer design exhibits 36% and 10% improvements in Ion and inverter delay, respectively.
{"title":"Corner spacer design for performance optimization of multi-gate InGaAs-OI FinFET with gate-to-source/drain underlap","authors":"V. Hu, Chang-Ting Lo, A. Sachid, P. Su, C. Hu","doi":"10.1109/VLSI-TSA.2016.7480515","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480515","url":null,"abstract":"Corner spacer design is investigated to improve the performance of multi-gate InGaAs-OI FinFET with gate-to-source/drain underlap compared with the all vacuum and all nitride spacer devices. All vacuum spacer devices with low permittivity reduce fringing capacitance and improve performance. However, for gate-to-source/drain underlap InGaAs-OI FinFET, all vacuum spacer device degrades source/drain resistance (Rsd) and ON current (Ion), thus exhibiting slight improvement in inverter delay compared with the all nitride spacer device. Corner spacer design comprising of high-k and low-k composite spacer is proposed to optimize Rsd and capacitance, and hence improve delay. Various lengths and heights of corner spacer for InGaAs-OI FinFET with different underlap length and fin height aspect ratio are investigated to optimized performance. The optimized corner spacer design is: (a) the length of corner spacer (Lcorner) is approximately equal to underlap length (Lun), and (b) the height of corner spacer (Hcorner) is proportional to the sum of fin height (Hfin) and gate oxide thickness (Tox). Compared with the all vacuum spacer InGaAs-OI FinFET with Lun = 6 nm, the optimized corner spacer design exhibits 36% and 10% improvements in Ion and inverter delay, respectively.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132558299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-25DOI: 10.1109/VLSI-TSA.2016.7480493
R. Pandey, R. Ghosh, S. Datta
In this work, we perform a detailed materials and device design evaluation for p-channel homo-junction and hetero-junction Tunnel FETs in Ge and GeSn material system. We start with atomistic level materials simulation using first principles density functional theory (DFT) and extend it to device level TCAD simulation. We show clearly the impact of tuning Sn composition to engineer the band structure and control the relative contribution of the direct and phonon assisted indirect band-to-band tunneling to design and demonstrate p-channel Tunnel FET in the Group IV system that are competitive with their III-V compound semiconductor counterparts.
{"title":"Band structure engineered Germanium-Tin (GeSn) p-channel tunnel transistors","authors":"R. Pandey, R. Ghosh, S. Datta","doi":"10.1109/VLSI-TSA.2016.7480493","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2016.7480493","url":null,"abstract":"In this work, we perform a detailed materials and device design evaluation for p-channel homo-junction and hetero-junction Tunnel FETs in Ge and GeSn material system. We start with atomistic level materials simulation using first principles density functional theory (DFT) and extend it to device level TCAD simulation. We show clearly the impact of tuning Sn composition to engineer the band structure and control the relative contribution of the direct and phonon assisted indirect band-to-band tunneling to design and demonstrate p-channel Tunnel FET in the Group IV system that are competitive with their III-V compound semiconductor counterparts.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134623350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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