Fault Diagnosis using Functional Fault Models for VHDL descriptions

Abstract

This paper describes algorithms for fault diagnosis of computer hardware modeled in VHDL [1,2,3,4]. Given a VHDL description, the compiler creates an internal representation. For fault diagnosis, a hierarchical approach using the stuck-at fault model at the first level and the arbitrary failure model at the second level, is used. The diagnosis algorithm reasons from first principles using constraint suspension.