G. Van den bosch, L. Breuil, A. Cacciato, A. Rothschild, M. Jurczak, J. van Houdt
{"title":"Investigation of Window Instability in Program/Erase Cycling of TANOS NAND Flash Memory","authors":"G. Van den bosch, L. Breuil, A. Cacciato, A. Rothschild, M. Jurczak, J. van Houdt","doi":"10.1109/IMW.2009.5090596","DOIUrl":null,"url":null,"abstract":"TANOS endurance is mainly governed by interface traps at the substrate-tunnel oxide interface, generated upon electrical stress, rather than by fixed charge in the tunnel oxide/blocking dielectric or by incomplete charge compensation in the nitride. As a result of acceptor resp. donor trap formation in the upper resp. lower half of the Si band gap, the V,h program/erase window monotonically shifts upward whereas the V fb window exhibits turn-around behavior. Interface trap generation rate is highest during the erase operation and depends also on the memory stack process.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"240 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"20","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE International Memory Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMW.2009.5090596","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 20
Abstract
TANOS endurance is mainly governed by interface traps at the substrate-tunnel oxide interface, generated upon electrical stress, rather than by fixed charge in the tunnel oxide/blocking dielectric or by incomplete charge compensation in the nitride. As a result of acceptor resp. donor trap formation in the upper resp. lower half of the Si band gap, the V,h program/erase window monotonically shifts upward whereas the V fb window exhibits turn-around behavior. Interface trap generation rate is highest during the erase operation and depends also on the memory stack process.
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