Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090601
L. Goux, J. Lisoni, L. Courtade, C. Muller, M. Jurczak, D. Wouters
The NiO resistive-switching memory is under investigation due to its attractive properties and scaling potential. In this paper, we evidence the possible coexistence of both the bipolar and unipolar switching modes in NiO films. The bipolar mode can be activated provided the oxidation time is limited so that O 2- movement through easy paths allows electrochemical reduction/oxidation, while the unipolar mode is favored for longer oxidation times associated with larger NiO cell resistance. The memory states in bipolar and unipolar modes are shown to have different electrical properties.
由于其极具吸引力的特性和扩展潜力，人们正在对氧化镍电阻开关存储器进行研究。在本文中，我们证明了氧化镍薄膜中可能同时存在双极和单极开关模式。双极模式可以在氧化时间有限的情况下被激活，这样 O 2- 就可以通过简单的路径进行电化学还原/氧化，而单极模式则在氧化时间较长、NiO 电池电阻较大的情况下更受青睐。双极模式和单极模式的记忆状态具有不同的电气特性。
{"title":"On the Bipolar and Unipolar Switching Mechanisms Observed in NiO Memory Cells Made by Thermal Oxidation of Ni","authors":"L. Goux, J. Lisoni, L. Courtade, C. Muller, M. Jurczak, D. Wouters","doi":"10.1109/IMW.2009.5090601","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090601","url":null,"abstract":"The NiO resistive-switching memory is under investigation due to its attractive properties and scaling potential. In this paper, we evidence the possible coexistence of both the bipolar and unipolar switching modes in NiO films. The bipolar mode can be activated provided the oxidation time is limited so that O 2- movement through easy paths allows electrochemical reduction/oxidation, while the unipolar mode is favored for longer oxidation times associated with larger NiO cell resistance. The memory states in bipolar and unipolar modes are shown to have different electrical properties.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126086946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090576
Y. Hsiao, H. Lue, K. Hsieh, Rich Liu, Chih-Yuan Lu
The interference and fringing field effects beyond sub-30 nm node charge-trapping(CT) NAND Flash are studied critically using 3D simulation. Due to the relatively large EOT (>15 nm) compared to the device dimension (F), the most severe interference comes from adjacent pass-gate WL bias disturb through the edge fringing field effect. On the other hand, the program charges in adjacent devices generate only minor interference effect (<200 mV) down to 25 nm node. Low-K spacer between WL's is very effective in suppressing the pass-gate interference due to the suppressed fringing field effect. For the first time we propose that low-K spacer can improve the short-channel effect as well as program/erase characteristics. The physical reason is that low-K spacer can confine the electrical field inside the channel thus improve the device performances. By suitably engineering the low-K spacer, p-well/junction and EOT we suggest that scaling of CT NAND Flash beyond 15 nm is quite feasible.
{"title":"A Study of Stored Charge Interference and Fringing Field Effects in Sub-30nm Charge-Trapping NAND Flash","authors":"Y. Hsiao, H. Lue, K. Hsieh, Rich Liu, Chih-Yuan Lu","doi":"10.1109/IMW.2009.5090576","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090576","url":null,"abstract":"The interference and fringing field effects beyond sub-30 nm node charge-trapping(CT) NAND Flash are studied critically using 3D simulation. Due to the relatively large EOT (>15 nm) compared to the device dimension (F), the most severe interference comes from adjacent pass-gate WL bias disturb through the edge fringing field effect. On the other hand, the program charges in adjacent devices generate only minor interference effect (<200 mV) down to 25 nm node. Low-K spacer between WL's is very effective in suppressing the pass-gate interference due to the suppressed fringing field effect. For the first time we propose that low-K spacer can improve the short-channel effect as well as program/erase characteristics. The physical reason is that low-K spacer can confine the electrical field inside the channel thus improve the device performances. By suitably engineering the low-K spacer, p-well/junction and EOT we suggest that scaling of CT NAND Flash beyond 15 nm is quite feasible.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125556088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090590
S. Puget, G. Bossu, C. Fenouiller-Beranger, P. Perreau, P. Masson, P. Mazoyer, P. Lorenzini, J. Portal, R. Bouchakour, T. Skotnicki
A Capacitorless IT-DRAM cell using gate-induced drain leakage (GIDL) current for write operation was demonstrated for the first time on FDSOI substrate, 9.5 nm silicon film and 19 nm BOX. 20 nm gate scaling improves 20% memory effect amplitude. GIDL mechanism allows low bias, low power, fast write time and does not affect intrinsic retention time. A similar value of 10 ms at 85degC is obtained like for impact ionization (II) optimised devices.
{"title":"FDSOI Floating Body Cell eDRAM Using Gate-Induced Drain-Leakage (GIDL) Write Current for High Speed and Low Power Applications","authors":"S. Puget, G. Bossu, C. Fenouiller-Beranger, P. Perreau, P. Masson, P. Mazoyer, P. Lorenzini, J. Portal, R. Bouchakour, T. Skotnicki","doi":"10.1109/IMW.2009.5090590","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090590","url":null,"abstract":"A Capacitorless IT-DRAM cell using gate-induced drain leakage (GIDL) current for write operation was demonstrated for the first time on FDSOI substrate, 9.5 nm silicon film and 19 nm BOX. 20 nm gate scaling improves 20% memory effect amplitude. GIDL mechanism allows low bias, low power, fast write time and does not affect intrinsic retention time. A similar value of 10 ms at 85degC is obtained like for impact ionization (II) optimised devices.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126998346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090575
S. Verma, G. Bersuker, D. Gilmer, A. Padovani, H. Park, A. Nainani, D. Heh, Jeff Huang, Jack Jiang, K. Parat, P. Kirsch, L. Larcher, H. Tseng, K. Saraswat, R. Jammy
We demonstrate for the first time a fluorine incorporated band- engineered (BE) tunnel oxide (SiO 2 /HfSiO/SiO 2 ) TANOS with excellent program / erase (P/E) characteristics and endurance to 10 5 cycles. Incorporating fluorine in the tunnel dielectric improves Si/SiO 2 interface resulting in excellent endurance of nearly constant over 3 V P/E window for at least 10 5 cycles. Fluorine also reduces interface state generation during retention by ~20%. Furthermore, Fluorine passivates bulk traps leading to as much as ~10times higher charge to breakdown (Q bd ) and ~10-50times lower interface state density (Dit). Fluorine passivation for BE-TANOS is significant because it improves reliability assisting implementation of TANOS flash NVM beyond the 20 nm node.
我们首次展示了含氟带工程(BE)隧道氧化物(sio2 /HfSiO/ sio2) TANOS具有优异的程序/擦除(P/E)特性和105次循环的耐久性。在隧道电介质中加入氟改善了Si/ sio2界面，从而获得了在3 V P/E窗口上几乎恒定的优异耐久性，至少105次循环。氟也减少界面状态的产生约20%的保留。此外，氟钝化体阱导致高达10倍的击穿电荷(qbd)和~10-50倍的界面态密度(Dit)降低。BE-TANOS的氟钝化非常重要，因为它提高了可靠性，有助于实现超过20 nm节点的TANOS闪存NVM。
{"title":"A Novel Fluorine Incorporated Band Engineered (BE) Tunnel (SiO2/ HfSiO/ SiO2) TANOS with Excellent Program/Erase & Endurance to 10^5 Cycles","authors":"S. Verma, G. Bersuker, D. Gilmer, A. Padovani, H. Park, A. Nainani, D. Heh, Jeff Huang, Jack Jiang, K. Parat, P. Kirsch, L. Larcher, H. Tseng, K. Saraswat, R. Jammy","doi":"10.1109/IMW.2009.5090575","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090575","url":null,"abstract":"We demonstrate for the first time a fluorine incorporated band- engineered (BE) tunnel oxide (SiO 2 /HfSiO/SiO 2 ) TANOS with excellent program / erase (P/E) characteristics and endurance to 10 5 cycles. Incorporating fluorine in the tunnel dielectric improves Si/SiO 2 interface resulting in excellent endurance of nearly constant over 3 V P/E window for at least 10 5 cycles. Fluorine also reduces interface state generation during retention by ~20%. Furthermore, Fluorine passivates bulk traps leading to as much as ~10times higher charge to breakdown (Q bd ) and ~10-50times lower interface state density (Dit). Fluorine passivation for BE-TANOS is significant because it improves reliability assisting implementation of TANOS flash NVM beyond the 20 nm node.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134547899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090571
M. Jeong, H. Kwon, Jong-Ho Lee
A new vertical NAND flash string with tube channel structure and top source contact has been proposed. The DC and program/erase characteristics of the proposed transistor is investigated using a 3-D TCAD simulation tool. This work is expected to show better P/E, retention, and reliability characteristics than Toshiba's structure.
{"title":"3-D Stacked NAND Flash String with Tube Channel Structure Using Si and SiGe Selective Etch Process","authors":"M. Jeong, H. Kwon, Jong-Ho Lee","doi":"10.1109/IMW.2009.5090571","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090571","url":null,"abstract":"A new vertical NAND flash string with tube channel structure and top source contact has been proposed. The DC and program/erase characteristics of the proposed transistor is investigated using a 3-D TCAD simulation tool. This work is expected to show better P/E, retention, and reliability characteristics than Toshiba's structure.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133883889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090605
D. C. Jackson, M. Nardone, V. Karpov, I. Karpov
The purpose of this work is to investigate the material and device properties of GST-based PCM by studying relaxation oscillations [1, 2]. Our experimental results relate oscillation characteristics to applied voltage, load resistance and device thickness.
{"title":"Relaxation Oscillation in GST-Based Phase Change Memory Devices","authors":"D. C. Jackson, M. Nardone, V. Karpov, I. Karpov","doi":"10.1109/IMW.2009.5090605","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090605","url":null,"abstract":"The purpose of this work is to investigate the material and device properties of GST-based PCM by studying relaxation oscillations [1, 2]. Our experimental results relate oscillation characteristics to applied voltage, load resistance and device thickness.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"8 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131725219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090598
G. Tallarida, N. Huby, B. Kutrzeba-Kotowska, Sabina Spiga, M. Arcari, Gyorgy Csaba, Paolo Lugli, A. Redaelli, R. Bez
ZnO-based Schottky junctions fabricated at low temperature are proposed as selectors for crossbar non-volatile memory devices. Rectifying ratio over 10 7 and forward current density as high as 10 4 A/cm 2 are reported. Results of the integration with NiO based switching memory elements are also shown.
{"title":"Low Temperature Rectifying Junctions for Crossbar Non-Volatile Memory Devices","authors":"G. Tallarida, N. Huby, B. Kutrzeba-Kotowska, Sabina Spiga, M. Arcari, Gyorgy Csaba, Paolo Lugli, A. Redaelli, R. Bez","doi":"10.1109/IMW.2009.5090598","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090598","url":null,"abstract":"ZnO-based Schottky junctions fabricated at low temperature are proposed as selectors for crossbar non-volatile memory devices. Rectifying ratio over 10\u0000 7\u0000 and forward current density as high as 10\u0000 4\u0000 A/cm\u0000 2\u0000 are reported. Results of the integration with NiO based switching memory elements are also shown.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117126085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090579
M. Bocquet, E. Vianello, G. Molas, L. Perniola, H. Grampeix, F. Martin, J. Colonna, A. Papon, P. Brianceau, M. Gely, B. De Salvo, G. Pananakakis, G. Ghibaudo, L. Selmi
The goal of this work is to give a clear physical comprehension of the charge loss mechanisms of SANOS (Si/Al 2 O 3 /Si 3 N 4 /SiO 2 /Si) memories. Retention at room and high temperature is investigated on different samples through experiments and theoretical modeling. We argue that at room temperature, the charge loss essentially results from the tunneling of the electrons trapped at the nitride interface, and the retention life time increases with the nitride thickness. On the contrary, at high temperature, the trapped charges in the nitride volume quickly redistribute, thanks to the thermal emission process, and they migrate to the nitride interface. Indeed, this result suggests that thin-nitride thicknesses in SANOS devices allow keeping a fast program/erase speed without degrading the retention at high temperature.
{"title":"An In-Depth Investigation of Physical Mechanisms Governing SANOS Memories Characteristics","authors":"M. Bocquet, E. Vianello, G. Molas, L. Perniola, H. Grampeix, F. Martin, J. Colonna, A. Papon, P. Brianceau, M. Gely, B. De Salvo, G. Pananakakis, G. Ghibaudo, L. Selmi","doi":"10.1109/IMW.2009.5090579","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090579","url":null,"abstract":"The goal of this work is to give a clear physical comprehension of the charge loss mechanisms of SANOS (Si/Al 2 O 3 /Si 3 N 4 /SiO 2 /Si) memories. Retention at room and high temperature is investigated on different samples through experiments and theoretical modeling. We argue that at room temperature, the charge loss essentially results from the tunneling of the electrons trapped at the nitride interface, and the retention life time increases with the nitride thickness. On the contrary, at high temperature, the trapped charges in the nitride volume quickly redistribute, thanks to the thermal emission process, and they migrate to the nitride interface. Indeed, this result suggests that thin-nitride thicknesses in SANOS devices allow keeping a fast program/erase speed without degrading the retention at high temperature.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123770278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090602
P. Blomme, J. de Vos, J. van Houdt
The scaling opportunities of the conventional SiO2 tunnel dielectric are very limited, leading to the impossibility to decrease the write and erase voltages of Flash memory, which is a major burden for floating gate Flash memory scaling. Reduction of the (effective) thickness of the interpoly dielectric can be obtained by the use of high-k materials [1], but reducing the effective thickness of the tunnel oxide requires the use of engineered tunneling barriers such as the crested barrier [2] or the VARIOT (variable oxide thickness) stack [3][4][5], the latter being used in this work. As has previously been shown [6][7], Al2O3 is the most promising high-k dielectric for the Flash cell gate stack. In this work, we evaluate the effect of different parameters (stack composition, deposition method, post-deposition treatment) on the reliability of Al2O3 based VARIOT dielectric stacks.
{"title":"Optimization of Al2O3 Based VARIOT Engineered Tunnel Dielectric for Floating Gate Flash Scaling","authors":"P. Blomme, J. de Vos, J. van Houdt","doi":"10.1109/IMW.2009.5090602","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090602","url":null,"abstract":"The scaling opportunities of the conventional SiO2 tunnel dielectric are very limited, leading to the impossibility to decrease the write and erase voltages of Flash memory, which is a major burden for floating gate Flash memory scaling. Reduction of the (effective) thickness of the interpoly dielectric can be obtained by the use of high-k materials [1], but reducing the effective thickness of the tunnel oxide requires the use of engineered tunneling barriers such as the crested barrier [2] or the VARIOT (variable oxide thickness) stack [3][4][5], the latter being used in this work. As has previously been shown [6][7], Al2O3 is the most promising high-k dielectric for the Flash cell gate stack. In this work, we evaluate the effect of different parameters (stack composition, deposition method, post-deposition treatment) on the reliability of Al2O3 based VARIOT dielectric stacks.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132642348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-05-10DOI: 10.1109/IMW.2009.5090581
H. Aochi
In this presentation, recent reports on three dimensional non-volatile memories are reviewed and their pros and cons are discussed. BiCS (Bit Cost Scalable) flash technology is focused as one of the most promising candidates for the future ultra high density storage devices.
{"title":"BiCS Flash as a Future 3D Non-Volatile Memory Technology for Ultra High Density Storage Devices","authors":"H. Aochi","doi":"10.1109/IMW.2009.5090581","DOIUrl":"https://doi.org/10.1109/IMW.2009.5090581","url":null,"abstract":"In this presentation, recent reports on three dimensional non-volatile memories are reviewed and their pros and cons are discussed. BiCS (Bit Cost Scalable) flash technology is focused as one of the most promising candidates for the future ultra high density storage devices.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130030417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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