{"title":"Low power 3D-integrated Solid-State Drive (SSD) with adaptive voltage generator","authors":"K. Takeuchi","doi":"10.1109/IMW.2010.5488397","DOIUrl":null,"url":null,"abstract":"A 3D-integrated Solid-State Drive (SSD with an adaptive program-voltage generator is introduced. The proposed boost converter is composed of a spiral inductor, a high-voltage MOS circuit, and an adaptive-frequency and duty-cycle (AFD) controller. The 5 × 5mm2 spiral inductor is implemented in an interposer. The high-voltage MOS circuit is fabricated with a matured NAND flash process. The AFD controller is manufactured with a conventional 0.18um low-voltage CMOS process. The AFD controller dynamically optimizes clock frequencies and duty cycles at different values, depending on the output voltage. As a result, the power consumption, rising time, and circuit area of the program-voltage generator decreases by 88%, 73%, and 85%, respectively. The total power consumption of the NAND flash memory decreases by 68%.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE International Memory Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMW.2010.5488397","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A 3D-integrated Solid-State Drive (SSD with an adaptive program-voltage generator is introduced. The proposed boost converter is composed of a spiral inductor, a high-voltage MOS circuit, and an adaptive-frequency and duty-cycle (AFD) controller. The 5 × 5mm2 spiral inductor is implemented in an interposer. The high-voltage MOS circuit is fabricated with a matured NAND flash process. The AFD controller is manufactured with a conventional 0.18um low-voltage CMOS process. The AFD controller dynamically optimizes clock frequencies and duty cycles at different values, depending on the output voltage. As a result, the power consumption, rising time, and circuit area of the program-voltage generator decreases by 88%, 73%, and 85%, respectively. The total power consumption of the NAND flash memory decreases by 68%.