Pub Date : 2010-05-16DOI: 10.1109/IMW.2010.5488386
Byeong-In Choe, Sung-Il Chang, Chang-seok Kang, Jintaek Park, Joohyuck Chung, Young-woo Park, Jungdal Choi, C. Chung
The local electron trapping in the select transistors used in the Charge Trap Flash (CTF) NAND was analyzed in depth for the first time in terms of operation conditions and gate spacer process. In this work, we examined the mechanism of swing degradation in the select transistors with TANOS (TaN-Al2O3-Si3N4-SiO2-Si) structure due to repetitive program/erase [P/E] operation. The swing degradation can be explained by the local electron trapping induced from electric field between select transistors and neighboring transistors. The local electron trapping in select transistors are well correlated to the saturation of threshold voltage in the erased cells. The erase Vth saturation appears to be caused by unfavorable backward tunneling of electrons from gate to the trap layer. The degradation in the select transistor is perfectly solved by decreasing the electric field during erase operation and keeping an appropriate distance between select transistors and neighboring transistors.
{"title":"A comprehensive study of degradation behavior of select transistors in the Charge Trap Flash memories","authors":"Byeong-In Choe, Sung-Il Chang, Chang-seok Kang, Jintaek Park, Joohyuck Chung, Young-woo Park, Jungdal Choi, C. Chung","doi":"10.1109/IMW.2010.5488386","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488386","url":null,"abstract":"The local electron trapping in the select transistors used in the Charge Trap Flash (CTF) NAND was analyzed in depth for the first time in terms of operation conditions and gate spacer process. In this work, we examined the mechanism of swing degradation in the select transistors with TANOS (TaN-Al2O3-Si3N4-SiO2-Si) structure due to repetitive program/erase [P/E] operation. The swing degradation can be explained by the local electron trapping induced from electric field between select transistors and neighboring transistors. The local electron trapping in select transistors are well correlated to the saturation of threshold voltage in the erased cells. The erase Vth saturation appears to be caused by unfavorable backward tunneling of electrons from gate to the trap layer. The degradation in the select transistor is perfectly solved by decreasing the electric field during erase operation and keeping an appropriate distance between select transistors and neighboring transistors.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"265 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123444725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-16DOI: 10.1109/IMW.2010.5488412
M. Deloge, B. Allard, P. Candelier, J. Damiens, E. Le-Roux, M. Rafik
The lifetime modeling of antifuse bit cells is studied using transient measurements. Firstly, the wearout current is successfully modeled as Fowler-Nordheim. Secondly, the TDDB power-law voltage acceleration model is validated down to 30 0ns for a stress voltage of 5.5 V. Lifetime results are compared with the Multi-Vibrational Hydrogen Release Model.
{"title":"Lifetime and wearout current modeling of ultra-thin oxide antifuse bitcells using transient characterization","authors":"M. Deloge, B. Allard, P. Candelier, J. Damiens, E. Le-Roux, M. Rafik","doi":"10.1109/IMW.2010.5488412","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488412","url":null,"abstract":"The lifetime modeling of antifuse bit cells is studied using transient measurements. Firstly, the wearout current is successfully modeled as Fowler-Nordheim. Secondly, the TDDB power-law voltage acceleration model is validated down to 30 0ns for a stress voltage of 5.5 V. Lifetime results are compared with the Multi-Vibrational Hydrogen Release Model.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128195919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-16DOI: 10.1109/IMW.2010.5488410
M. Jeong, Joo-Wan Lee, I. Cho, Byung-Gook Park, Hyungcheol Shin, Jang-Sik Lee
We have investigated ID-VGS characteristic of proposed 3-D stacked NAND flash string with common gate structure and a shield layer. The body cross-talk problem was eliminated completely. We think proposed structure and its modification will be very promising candidate for future high density NAND flash memory.
{"title":"Novel 3-D stacked NAND flash string without body cross-talk effect","authors":"M. Jeong, Joo-Wan Lee, I. Cho, Byung-Gook Park, Hyungcheol Shin, Jang-Sik Lee","doi":"10.1109/IMW.2010.5488410","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488410","url":null,"abstract":"We have investigated ID-VGS characteristic of proposed 3-D stacked NAND flash string with common gate structure and a shield layer. The body cross-talk problem was eliminated completely. We think proposed structure and its modification will be very promising candidate for future high density NAND flash memory.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132061929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-16DOI: 10.1109/IMW.2010.5488309
G. Molas, J. Colonna, R. Kies, D. Belhachemi, M. Bocquet, M. Gely, V. Vidal, P. Brianceau, L. Vandroux, G. Ghibaudo, B. De Salvo
This paper presents an in-depth investigation of the electrical properties of charge trap memories with AlN based storage layers. The memory performance and reliability are studied in details and compared with the ones of a reference device using standard Si3N4 as storage layer. An engineered charge trapping layer is also proposed, made by an AlN/Si3N4 double layer, which shows reduced program/erase voltages, combined with 106 excellent endurance and good retention (ΔVT>5V after 10 years at 125°C).
{"title":"Investigation of charge-trap memories with AlN based band engineered storage layers","authors":"G. Molas, J. Colonna, R. Kies, D. Belhachemi, M. Bocquet, M. Gely, V. Vidal, P. Brianceau, L. Vandroux, G. Ghibaudo, B. De Salvo","doi":"10.1109/IMW.2010.5488309","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488309","url":null,"abstract":"This paper presents an in-depth investigation of the electrical properties of charge trap memories with AlN based storage layers. The memory performance and reliability are studied in details and compared with the ones of a reference device using standard Si<sub>3</sub>N<sub>4</sub> as storage layer. An engineered charge trapping layer is also proposed, made by an AlN/Si<sub>3</sub>N<sub>4</sub> double layer, which shows reduced program/erase voltages, combined with 10<sup>6</sup> excellent endurance and good retention (ΔV<sub>T</sub>>5V after 10 years at 125°C).","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130963579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-16DOI: 10.1109/IMW.2010.5488391
Sang-Yun Lee, D. Schroder
3D ICs for high-density memories have significant benefits compared to conventional memories. The first one is high productivity. An area for memory arrays is not required on the semiconductor substrate and the area for the memory control logic can be further reduced for an optimized logic process. Hence, about 4 times more die-per-wafer can be expected for DRAMs with a cell efficiency of about 50%, leading to reduced fab tool investment with increased productivity. Furthermore, the process is optimized for both logic and memory cells because they are processed sequentially. It is well known that processes for logic and memory, especially DRAM and flash, are not compatible. Using 3D ICs, process incompatibility problems are easily solved and SoC (System-on-a-Chip) can be implemented with various embedded memories. An additional advantage is the small form factor. As die sizes shrink for 3D ICs, the yield will increase rapidly, especially important for FPGAs with distributed memories and high-performance CPUs with large cache memories. 3D ICs for high-density memories will extend the lifespan of low-cost CMOS memories.
{"title":"3D IC architecture for high density memories","authors":"Sang-Yun Lee, D. Schroder","doi":"10.1109/IMW.2010.5488391","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488391","url":null,"abstract":"3D ICs for high-density memories have significant benefits compared to conventional memories. The first one is high productivity. An area for memory arrays is not required on the semiconductor substrate and the area for the memory control logic can be further reduced for an optimized logic process. Hence, about 4 times more die-per-wafer can be expected for DRAMs with a cell efficiency of about 50%, leading to reduced fab tool investment with increased productivity. Furthermore, the process is optimized for both logic and memory cells because they are processed sequentially. It is well known that processes for logic and memory, especially DRAM and flash, are not compatible. Using 3D ICs, process incompatibility problems are easily solved and SoC (System-on-a-Chip) can be implemented with various embedded memories. An additional advantage is the small form factor. As die sizes shrink for 3D ICs, the yield will increase rapidly, especially important for FPGAs with distributed memories and high-performance CPUs with large cache memories. 3D ICs for high-density memories will extend the lifespan of low-cost CMOS memories.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129171234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-16DOI: 10.1109/IMW.2010.5488325
A. Driskill-Smith, S. Watts, D. Apalkov, D. Druist, X. Tang, Z. Diao, X. Luo, A. Ong, V. Nikitin, E. Chen
STT-RAM (Spin-Transfer Torque Random Access Memory) is a fast (≪10 ns), scalable, durable, non-volatile memory technology that is easily embedded in standard CMOS processes. An STT-RAM memory cell consists of an access transistor and a magnetic tunnel junction (MTJ) storage element (Figure 1). The minimum area of a single-level STT-RAM cell is 6 F2, which is competitive with DRAM and NOR Flash, and superior to SRAM. Even smaller effective unit cell areas are projected for multi-level cell architectures.
{"title":"Non-volatile Spin-Transfer Torque RAM (STT-RAM): An analysis of chip data, thermal stability and scalability","authors":"A. Driskill-Smith, S. Watts, D. Apalkov, D. Druist, X. Tang, Z. Diao, X. Luo, A. Ong, V. Nikitin, E. Chen","doi":"10.1109/IMW.2010.5488325","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488325","url":null,"abstract":"STT-RAM (Spin-Transfer Torque Random Access Memory) is a fast (≪10 ns), scalable, durable, non-volatile memory technology that is easily embedded in standard CMOS processes. An STT-RAM memory cell consists of an access transistor and a magnetic tunnel junction (MTJ) storage element (Figure 1). The minimum area of a single-level STT-RAM cell is 6 F2, which is competitive with DRAM and NOR Flash, and superior to SRAM. Even smaller effective unit cell areas are projected for multi-level cell architectures.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126647253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-16DOI: 10.1109/IMW.2010.5488403
Sung-Rae Kim, K. Han, Kin-Sing Lee, Rophina Li, J. Wolfman, Tae-Hoon Kim, Patty Liu, Hyuk Kim, P. Lee, Yu Wang, Yingbo Jia, F. Dhaoui, F. Hawley, Huan-Chung Tseng
High speed array architecture and cell optimization in the Uniform Channel Program and Erase (UCPE) floating gate 2 transistor (2T)-embedded flash cell (eFlash) are investigated. It is important to optimize select gate (SG) channel length from 2T-eFlash test array when CG flash device width/length and SG length are pre-determined by other constraints. SG-punch through (PT) driven Gate Disturb (GD) and Gate Induced Drain Leakage current (GIDL) driven GD must be simultaneously studied to determine the optimum CG and SG spacing. For the applications requiring thick tunnel oxide (10nm) such as automotive products, the conductivities of the Sector Select Gate (SSG) device and Control Gate (CG) flash device are critical for read performance. A double SSG scheme per sector and common metal source line architecture were introduced. In this paper, we report our investigation results to optimize 2T eFlash cell design and array architecture to achieve high performance eFlash operation without sacrificing reliability within the constraint of embedding a flash process in the 65nm standard logic process.
{"title":"High performance 65nm 2T-embedded Flash memory for high reliability SOC applications","authors":"Sung-Rae Kim, K. Han, Kin-Sing Lee, Rophina Li, J. Wolfman, Tae-Hoon Kim, Patty Liu, Hyuk Kim, P. Lee, Yu Wang, Yingbo Jia, F. Dhaoui, F. Hawley, Huan-Chung Tseng","doi":"10.1109/IMW.2010.5488403","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488403","url":null,"abstract":"High speed array architecture and cell optimization in the Uniform Channel Program and Erase (UCPE) floating gate 2 transistor (2T)-embedded flash cell (eFlash) are investigated. It is important to optimize select gate (SG) channel length from 2T-eFlash test array when CG flash device width/length and SG length are pre-determined by other constraints. SG-punch through (PT) driven Gate Disturb (GD) and Gate Induced Drain Leakage current (GIDL) driven GD must be simultaneously studied to determine the optimum CG and SG spacing. For the applications requiring thick tunnel oxide (10nm) such as automotive products, the conductivities of the Sector Select Gate (SSG) device and Control Gate (CG) flash device are critical for read performance. A double SSG scheme per sector and common metal source line architecture were introduced. In this paper, we report our investigation results to optimize 2T eFlash cell design and array architecture to achieve high performance eFlash operation without sacrificing reliability within the constraint of embedding a flash process in the 65nm standard logic process.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121557253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-16DOI: 10.1109/IMW.2010.5488319
S. Kawabata, Mitsuru Nakura, S. Yamazaki, T. Shibuya, Y. Inoue, Junya Onishi, Yoshiaki Tabuchi, Y. Tamai, Y. Yaoi, K. Ishihara, Y. Ohta, H. Shima, H. Akinaga, Natsuki Fukuda, Hidenao Kurihara, Yoshiaki Yoshida, Y. Kokaze, Y. Nishioka, K. Suu, K. Nakayama, A. Kitagawa, S. Ohnishi, N. Awaya
This paper presents the process integration and device technology for the Resistance RAM(RRAM) memory array using a CoOx film and a recess structure as a resistor, which is capable of low voltage, high speed and low current operation. The resistance of the CoOx film and its uniformity are strongly dependent on the film quality, which is optimized by controlling the O2 gas flow rate during the film deposition. We demonstrate the basic write and read operation of the 128Kbits memory array by developing the novel process integration technology and optimizing the test algorism.
{"title":"CoOx-RRAM memory cell technology using recess structure for 128Kbits memory array","authors":"S. Kawabata, Mitsuru Nakura, S. Yamazaki, T. Shibuya, Y. Inoue, Junya Onishi, Yoshiaki Tabuchi, Y. Tamai, Y. Yaoi, K. Ishihara, Y. Ohta, H. Shima, H. Akinaga, Natsuki Fukuda, Hidenao Kurihara, Yoshiaki Yoshida, Y. Kokaze, Y. Nishioka, K. Suu, K. Nakayama, A. Kitagawa, S. Ohnishi, N. Awaya","doi":"10.1109/IMW.2010.5488319","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488319","url":null,"abstract":"This paper presents the process integration and device technology for the Resistance RAM(RRAM) memory array using a CoOx film and a recess structure as a resistor, which is capable of low voltage, high speed and low current operation. The resistance of the CoOx film and its uniformity are strongly dependent on the film quality, which is optimized by controlling the O2 gas flow rate during the film deposition. We demonstrate the basic write and read operation of the 128Kbits memory array by developing the novel process integration technology and optimizing the test algorism.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130872934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-16DOI: 10.1109/IMW.2010.5488383
S. Cui, D. Eun, B. Marinkovic, C. Peng, Xiao Pan, Xiao Sun, H. Koser, T. Ma
We have shown that the metal-PZT-Al2O3 memory stack exhibits much larger than usual memory window, in the direction of charge-trapping effect (which is opposite to the polarization switching effect) which we attribute to the enhanced charge injection due to the large polarization field of the PZT. Other attractive properties such as excellent endurance characteristics and good retention make the metalPZT-Al2O3 memory stack a promising candidate for nonvolatile memory technology. Although the memory stack used in this study contains relatively thick PZT that necessitates high P/E voltages, our preliminary results have shown much lower P/E voltages for thinner PZT, and results for such scaled memory stacks will be reported at the conference.
{"title":"The dual role of PZT in metal-PZT-Al2O3 structure for nonvolatile memory cell","authors":"S. Cui, D. Eun, B. Marinkovic, C. Peng, Xiao Pan, Xiao Sun, H. Koser, T. Ma","doi":"10.1109/IMW.2010.5488383","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488383","url":null,"abstract":"We have shown that the metal-PZT-Al2O3 memory stack exhibits much larger than usual memory window, in the direction of charge-trapping effect (which is opposite to the polarization switching effect) which we attribute to the enhanced charge injection due to the large polarization field of the PZT. Other attractive properties such as excellent endurance characteristics and good retention make the metalPZT-Al2O3 memory stack a promising candidate for nonvolatile memory technology. Although the memory stack used in this study contains relatively thick PZT that necessitates high P/E voltages, our preliminary results have shown much lower P/E voltages for thinner PZT, and results for such scaled memory stacks will be reported at the conference.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"356 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133724401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-16DOI: 10.1109/IMW.2010.5488405
Sunyeong Lee, J. Jang, J. Shin, H. Kim, H. Bae, D. Yun, D. Kim, D. Kim
We propose a novel SiGe superlattice band-gap engineered (SBE) capacitorless dynamic random access memory (DRAM) cell with the 30 nm channel by the 2D TCAD simulation. The SBE capacitorless DRAM cell used a common source structure and different metal layers for the top gate word line from the bottom gate word line to realize the 4F2 (0.0036 µm2) feature size. From the 2D TCAD simulation of the SBE capacitorless DRAM cell, thanks to both the Si0.8Ge0.2 quantum well and SiO2 physical energy barrier, we obtained the sensing margin of 6.4 µA and the retention time of 15 msec.
{"title":"A novel superlattice band-gap engineered (SBE) capacitorless DRAM cell with extremely short channel length down to 30 nm","authors":"Sunyeong Lee, J. Jang, J. Shin, H. Kim, H. Bae, D. Yun, D. Kim, D. Kim","doi":"10.1109/IMW.2010.5488405","DOIUrl":"https://doi.org/10.1109/IMW.2010.5488405","url":null,"abstract":"We propose a novel SiGe superlattice band-gap engineered (SBE) capacitorless dynamic random access memory (DRAM) cell with the 30 nm channel by the 2D TCAD simulation. The SBE capacitorless DRAM cell used a common source structure and different metal layers for the top gate word line from the bottom gate word line to realize the 4F<sup>2</sup> (0.0036 µm<sup>2</sup>) feature size. From the 2D TCAD simulation of the SBE capacitorless DRAM cell, thanks to both the Si<inf>0.8</inf>Ge<inf>0.2</inf> quantum well and SiO<inf>2</inf> physical energy barrier, we obtained the sensing margin of 6.4 µA and the retention time of 15 msec.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133489223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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