TWO-STAGE FAULT LOCATION

P. Ryan, S. Rawat, W. Fuchs
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引用次数: 80

Abstract

A two-stage procedure for locating VLSI faults is presented. The approach utilizes dynamic fault dictionaries, test set partitioning, and reduced fault lists to achieve a reduction in size and complexity over classic static fault dictionaries. An industrial implementation is reported in which faults were injected and diagnosed in a VLSI chip and the perjiormunce of two-stage fault location was measured.
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两级故障定位
提出了一种两阶段的超大规模集成电路故障定位方法。该方法利用动态故障字典、测试集分区和简化的故障列表来实现与经典静态故障字典相比减小大小和复杂性的目的。本文报道了在超大规模集成电路芯片中进行故障注入和诊断,并测量了两级故障定位的性能。
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REAL-TIME DATA COMPARISON FOR GIGAHERTZ DIGITAL TEST REFINED BOUNDS ON SIGNATURE ANALYSIS ALIASING FOR RANDOM TESTING IMPLEMENTING BOUNDARY-SCAN AND PSEUDO-RANDOM BIST IN AN ASYNCHRONOUS TRANSFER MODE SWITCH ADVANCED MIXED SIGNAL TESTING BY DSP LOCALIZED TESTER AN IEEE 1149.1 BASED LOGIC/SIGNATURE ANALYZER IN A CHIP
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