Failure Analysis of 65nm CMOS Integrated Nanoscale ReRAM Devices on a 300mm Wafer Platform

Abstract

Device failure can lead to operation instability and application performance degradation. To avoid this, restricting operational parameters can optimize long-term device reliability; however, to fully maximize device performance and capability a comprehensive failure analysis study is required. In this work we observed the regions of operation failure concerning current, voltage, and temperature stress on integrated CMOS/ReRAM memory cells. Voltage and current stresses were reported to show sharp device failure due to changes in conduction and energy mismatch, while temperature stress affected long-term device performance. This analysis will allow a greater grasp of parameter usage for future ReRAM based memory.