Pub Date : 2022-10-09DOI: 10.1109/IIRW56459.2022.10032748
K. Tselios, T. Knobloch, J. Michl, Dominic Waldhoer, C. Schleich, E. Ioannidis, H. Enichlmair, R. Minixhofer, T. Grasser, M. Waltl
The reliable operation of MOS transistors is affected by charge trapping at defects located inside the oxide and at the oxide/semiconductor interface. Each of the single defects can capture and emit a charge, alter the device electrostatics and thus affect the device behavior, which can be observed as a drift of the threshold voltage. Understanding the physical mechanisms of charge trapping and the dependencies of the threshold voltage drifts on the device parameters is crucial for reliable operation of modern transistors and the implementation of future technology nodes. An enhanced understanding can be developed by performing electrical measurements on nanoscale devices which allow to detect discrete steps in the measured drain current which correspond to emission events of charges, previously captured at single defects. Using measurements on large sets of devices, statistical distributions of step heights can be created to study the dependence of statistical quantities, like the link between the average threshold shift of a single emission event and the lateral device dimensions. From our measurements on commercial pMOS and nMOS devices we found that the dependence of the average step height on $W times sqrt L $ allows to describe the data accurately for a wide range of gate widths and lengths while the most widely used dependence on the device area fails to provide a good agreement.
氧化物内部和氧化物/半导体界面缺陷处的电荷俘获影响MOS晶体管的可靠工作。每个单个缺陷都可以捕获并发射电荷，改变器件的静电，从而影响器件的行为，这可以观察到阈值电压的漂移。了解电荷捕获的物理机制和阈值电压漂移对器件参数的依赖关系对于现代晶体管的可靠运行和未来技术节点的实现至关重要。通过在纳米级器件上进行电测量，可以进一步加深对漏极电流的理解，这些漏极电流对应于先前在单个缺陷上捕获的电荷发射事件。通过对大量设备的测量，可以创建阶跃高度的统计分布，以研究统计量的依赖性，例如单个发射事件的平均阈值位移与横向设备尺寸之间的联系。从我们对商用pMOS和nMOS器件的测量中，我们发现平均阶跃高度对W 乘以sqrt L $的依赖关系允许在很宽的栅极宽度和长度范围内准确地描述数据，而最广泛使用的对器件面积的依赖关系未能提供很好的一致性。
{"title":"Impact of Single Defects on NBTI and PBTI Recovery in SiO2 Transistors","authors":"K. Tselios, T. Knobloch, J. Michl, Dominic Waldhoer, C. Schleich, E. Ioannidis, H. Enichlmair, R. Minixhofer, T. Grasser, M. Waltl","doi":"10.1109/IIRW56459.2022.10032748","DOIUrl":"https://doi.org/10.1109/IIRW56459.2022.10032748","url":null,"abstract":"The reliable operation of MOS transistors is affected by charge trapping at defects located inside the oxide and at the oxide/semiconductor interface. Each of the single defects can capture and emit a charge, alter the device electrostatics and thus affect the device behavior, which can be observed as a drift of the threshold voltage. Understanding the physical mechanisms of charge trapping and the dependencies of the threshold voltage drifts on the device parameters is crucial for reliable operation of modern transistors and the implementation of future technology nodes. An enhanced understanding can be developed by performing electrical measurements on nanoscale devices which allow to detect discrete steps in the measured drain current which correspond to emission events of charges, previously captured at single defects. Using measurements on large sets of devices, statistical distributions of step heights can be created to study the dependence of statistical quantities, like the link between the average threshold shift of a single emission event and the lateral device dimensions. From our measurements on commercial pMOS and nMOS devices we found that the dependence of the average step height on $W times sqrt L $ allows to describe the data accurately for a wide range of gate widths and lengths while the most widely used dependence on the device area fails to provide a good agreement.","PeriodicalId":446436,"journal":{"name":"2022 IEEE International Integrated Reliability Workshop (IIRW)","volume":"188 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121728254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/IIRW56459.2022.10032757
Andreas Martin, Lukáš Valdman, Benjamin Hamilton Stafford, H. Nielen
Anomalous NBTI degradation characteristics have been observed for pMOS transistors which had experienced plasma processing induced charging damage. This is a critical topic for correct NBTI lifetime predictions from antenna transistor structures with PID for p-type MOS and FinFET transistors with various thicknesses of SiO2 or high-K gate dielectrics. Examples from the literature also depict this NBTI anomaly. A qualitative charge trapping model is described for root cause analysis. A proposed methodology demonstrates the correction of NBTI data from antenna transistor structures with PID.
{"title":"Anomaly of NBTI data for PMOS transistors degraded by plasma processing induced charging damage (PID)","authors":"Andreas Martin, Lukáš Valdman, Benjamin Hamilton Stafford, H. Nielen","doi":"10.1109/IIRW56459.2022.10032757","DOIUrl":"https://doi.org/10.1109/IIRW56459.2022.10032757","url":null,"abstract":"Anomalous NBTI degradation characteristics have been observed for pMOS transistors which had experienced plasma processing induced charging damage. This is a critical topic for correct NBTI lifetime predictions from antenna transistor structures with PID for p-type MOS and FinFET transistors with various thicknesses of SiO2 or high-K gate dielectrics. Examples from the literature also depict this NBTI anomaly. A qualitative charge trapping model is described for root cause analysis. A proposed methodology demonstrates the correction of NBTI data from antenna transistor structures with PID.","PeriodicalId":446436,"journal":{"name":"2022 IEEE International Integrated Reliability Workshop (IIRW)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134114149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/IIRW56459.2022.10032736
Paul Stampfer, G. Meinhardt, T. Grasser, M. Waltl
Deep Trench Isolation (DTI) is a common termination technique in optoelectronics to minimize cross-talk between single devices fabricated on the same chip. However, DTI can also affect the performance of optoelectronic devices. In this work we simulate and model the influence of minority carrier recombination at the DTI interface on the quantum efficiency, i.e. responsivity, of Si photodetectors. We demonstrate that DTI interface recombination is a non-linear effect with respect to the applied irradiance and causes a non-linear response of the photodetector, which must be avoided for certain applications. Furthermore, we show that sufficiently high positive or negative fixed oxide charges can improve device performance by reducing the DTI interface recombination. To maintain the benefit of electrical cross-talk minimization in combination with an almost linear responsivity we propose a structure terminated with lateral deep trench metal oxide semiconductor capacitors (DTMOSCAPs) to control the passivation of the DTI interface by an applied gate bias. By means of TCAD simulations, we show that such a device is superior to default DTI structures in terms of responsivity as well as linearity.
{"title":"Simulating and Modeling the Influence of Deep Trench Interface Recombination on Si Photodiodes","authors":"Paul Stampfer, G. Meinhardt, T. Grasser, M. Waltl","doi":"10.1109/IIRW56459.2022.10032736","DOIUrl":"https://doi.org/10.1109/IIRW56459.2022.10032736","url":null,"abstract":"Deep Trench Isolation (DTI) is a common termination technique in optoelectronics to minimize cross-talk between single devices fabricated on the same chip. However, DTI can also affect the performance of optoelectronic devices. In this work we simulate and model the influence of minority carrier recombination at the DTI interface on the quantum efficiency, i.e. responsivity, of Si photodetectors. We demonstrate that DTI interface recombination is a non-linear effect with respect to the applied irradiance and causes a non-linear response of the photodetector, which must be avoided for certain applications. Furthermore, we show that sufficiently high positive or negative fixed oxide charges can improve device performance by reducing the DTI interface recombination. To maintain the benefit of electrical cross-talk minimization in combination with an almost linear responsivity we propose a structure terminated with lateral deep trench metal oxide semiconductor capacitors (DTMOSCAPs) to control the passivation of the DTI interface by an applied gate bias. By means of TCAD simulations, we show that such a device is superior to default DTI structures in terms of responsivity as well as linearity.","PeriodicalId":446436,"journal":{"name":"2022 IEEE International Integrated Reliability Workshop (IIRW)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124574416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/IIRW56459.2022.10032747
Maximilian Liehr, Jubin Hazra, K. Beckmann, N. Cady
Device failure can lead to operation instability and application performance degradation. To avoid this, restricting operational parameters can optimize long-term device reliability; however, to fully maximize device performance and capability a comprehensive failure analysis study is required. In this work we observed the regions of operation failure concerning current, voltage, and temperature stress on integrated CMOS/ReRAM memory cells. Voltage and current stresses were reported to show sharp device failure due to changes in conduction and energy mismatch, while temperature stress affected long-term device performance. This analysis will allow a greater grasp of parameter usage for future ReRAM based memory.
{"title":"Failure Analysis of 65nm CMOS Integrated Nanoscale ReRAM Devices on a 300mm Wafer Platform","authors":"Maximilian Liehr, Jubin Hazra, K. Beckmann, N. Cady","doi":"10.1109/IIRW56459.2022.10032747","DOIUrl":"https://doi.org/10.1109/IIRW56459.2022.10032747","url":null,"abstract":"Device failure can lead to operation instability and application performance degradation. To avoid this, restricting operational parameters can optimize long-term device reliability; however, to fully maximize device performance and capability a comprehensive failure analysis study is required. In this work we observed the regions of operation failure concerning current, voltage, and temperature stress on integrated CMOS/ReRAM memory cells. Voltage and current stresses were reported to show sharp device failure due to changes in conduction and energy mismatch, while temperature stress affected long-term device performance. This analysis will allow a greater grasp of parameter usage for future ReRAM based memory.","PeriodicalId":446436,"journal":{"name":"2022 IEEE International Integrated Reliability Workshop (IIRW)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123966075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/IIRW56459.2022.10032750
Y. Raffel, M. Drescher, R. Olivo, M. Lederer, R. Hoffmann, L. Pirro, T. Chohan, T. Kämpfe, K. Seidel, S. De, J. Heitmann
A major reliability concern in modern high-k field effect transistors (FETs) resembles the defect density distribution within the hafnium oxide layer as well as its interaction with the interfacial oxide layer. For a deeper understanding of the distribution of charged traps both energetically as well as spatially, it is essential to upgrade from a two level charge pumping scheme to a three level scheme. Through variation in pulse width and amplitude of a subsequent second level pulse, defect energy and location can be extracted inside the gate stack, which is important to understand the overall reliability impact of these traps onto the device properties.
{"title":"Three Level Charge Pumping On Dielectric Hafnium Oxide Gate","authors":"Y. Raffel, M. Drescher, R. Olivo, M. Lederer, R. Hoffmann, L. Pirro, T. Chohan, T. Kämpfe, K. Seidel, S. De, J. Heitmann","doi":"10.1109/IIRW56459.2022.10032750","DOIUrl":"https://doi.org/10.1109/IIRW56459.2022.10032750","url":null,"abstract":"A major reliability concern in modern high-k field effect transistors (FETs) resembles the defect density distribution within the hafnium oxide layer as well as its interaction with the interfacial oxide layer. For a deeper understanding of the distribution of charged traps both energetically as well as spatially, it is essential to upgrade from a two level charge pumping scheme to a three level scheme. Through variation in pulse width and amplitude of a subsequent second level pulse, defect energy and location can be extracted inside the gate stack, which is important to understand the overall reliability impact of these traps onto the device properties.","PeriodicalId":446436,"journal":{"name":"2022 IEEE International Integrated Reliability Workshop (IIRW)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124861963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/IIRW56459.2022.10032764
Tobias Reiter, X. Klemenschits, L. Filipovic
A novel framework for the simulation of plasma-induced damage based on an adapted binary collision model is presented. The presented approach allows for the physical simulation of plasma damage during transient dry etch process simulations. The developed model is applied to two different substrate geometries, capturing plasma-induced damage caused by ion bombardment throughout the transient etch simulation. A detailed comparison to experimental data shows that even this simple collision model produces accurate results and thus provides a description of complex damage profiles for the entire duration of the processing step.
{"title":"Modeling Plasma-Induced Damage During the Dry Etching of Silicon","authors":"Tobias Reiter, X. Klemenschits, L. Filipovic","doi":"10.1109/IIRW56459.2022.10032764","DOIUrl":"https://doi.org/10.1109/IIRW56459.2022.10032764","url":null,"abstract":"A novel framework for the simulation of plasma-induced damage based on an adapted binary collision model is presented. The presented approach allows for the physical simulation of plasma damage during transient dry etch process simulations. The developed model is applied to two different substrate geometries, capturing plasma-induced damage caused by ion bombardment throughout the transient etch simulation. A detailed comparison to experimental data shows that even this simple collision model produces accurate results and thus provides a description of complex damage profiles for the entire duration of the processing step.","PeriodicalId":446436,"journal":{"name":"2022 IEEE International Integrated Reliability Workshop (IIRW)","volume":"285 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132452149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/IIRW56459.2022.10032753
T. Rizzi, Andrea Baroni, A. Glukhov, D. Bertozzi, C. Wenger, D. Ielmini, C. Zambelli
Resistive Random Access Memory (RRAM) devices hold promise to improve the performance of full-CMOS Field Programmable Gate Arrays (FPGAs) exploiting their non-volatility, multilevel nature, small area requirement, and CMOS compatibility for the routing interconnections. Unfortunately, the adoption of this emerging technology is hindered by its intrinsic resistance stochastic behavior. In this work, we investigate how Process-Voltage-Temperature (PVT) variations affect the energy and propagation delay of 4T1R MUX circuits. The comparison with traditional CMOS implementations reveals that for large-sized MUX the RRAM technology is more energy efficient and robust to PVT variations.
{"title":"Exploring Process-Voltage-Temperature Variations Impact on 4T1R Multiplexers for Energy-aware Resistive RAM-based FPGAs","authors":"T. Rizzi, Andrea Baroni, A. Glukhov, D. Bertozzi, C. Wenger, D. Ielmini, C. Zambelli","doi":"10.1109/IIRW56459.2022.10032753","DOIUrl":"https://doi.org/10.1109/IIRW56459.2022.10032753","url":null,"abstract":"Resistive Random Access Memory (RRAM) devices hold promise to improve the performance of full-CMOS Field Programmable Gate Arrays (FPGAs) exploiting their non-volatility, multilevel nature, small area requirement, and CMOS compatibility for the routing interconnections. Unfortunately, the adoption of this emerging technology is hindered by its intrinsic resistance stochastic behavior. In this work, we investigate how Process-Voltage-Temperature (PVT) variations affect the energy and propagation delay of 4T1R MUX circuits. The comparison with traditional CMOS implementations reveals that for large-sized MUX the RRAM technology is more energy efficient and robust to PVT variations.","PeriodicalId":446436,"journal":{"name":"2022 IEEE International Integrated Reliability Workshop (IIRW)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132995596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/IIRW56459.2022.10077885
F. Cacho, A. Bravaix, T. G. Seybou, H. Pitard, X. Federspiel, T. Kumar, F. Giner, A. Michard, D. Celeste, B. Miller, V. Dhanda, A. Varshney, V. Tripathi, J. Kumar
Aging phenomena are first evidenced at device level to cell level considering a precise knowledge of the leading degradation mechanisms and interactions useful for processing optimization focusing performance vs. reliability requirements. Digital to analog circuits are then studied for product qualification based on the former results that needs specific methodologies adapted case by case with mission profile and the correlation between sensing parameter, accelerating factors for lifetime margin. This represents huge challenges for operational lifetime determination, considering top down and bottom up consistencies for relevant product qualification.
{"title":"Device Reliability to Circuit Qualification: Insights and Challenges","authors":"F. Cacho, A. Bravaix, T. G. Seybou, H. Pitard, X. Federspiel, T. Kumar, F. Giner, A. Michard, D. Celeste, B. Miller, V. Dhanda, A. Varshney, V. Tripathi, J. Kumar","doi":"10.1109/IIRW56459.2022.10077885","DOIUrl":"https://doi.org/10.1109/IIRW56459.2022.10077885","url":null,"abstract":"Aging phenomena are first evidenced at device level to cell level considering a precise knowledge of the leading degradation mechanisms and interactions useful for processing optimization focusing performance vs. reliability requirements. Digital to analog circuits are then studied for product qualification based on the former results that needs specific methodologies adapted case by case with mission profile and the correlation between sensing parameter, accelerating factors for lifetime margin. This represents huge challenges for operational lifetime determination, considering top down and bottom up consistencies for relevant product qualification.","PeriodicalId":446436,"journal":{"name":"2022 IEEE International Integrated Reliability Workshop (IIRW)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133284140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/IIRW56459.2022.10032761
K. Henderson, Brian Hulse, M. Styduhar, Peter Michelson
Weaknesses in electrostatic discharge (ESD) connection paths directly contribute to field failures if they are not properly identified and fixed pre-silicon. Although traditional verification tools such as design rule checking (DRC), layout vs. schematic (LVS) verification and electrical rule checking (ERC) are still required in an integrated circuit (IC) verification flow, they can no longer be the only tools used. This work demonstrates the importance of adding comprehensive reliability checking to the overall IC verification flow to accurately identify reliability issues that cannot be found using traditional verification methods.
{"title":"Ensuring robust ESD design with comprehensive reliability verification","authors":"K. Henderson, Brian Hulse, M. Styduhar, Peter Michelson","doi":"10.1109/IIRW56459.2022.10032761","DOIUrl":"https://doi.org/10.1109/IIRW56459.2022.10032761","url":null,"abstract":"Weaknesses in electrostatic discharge (ESD) connection paths directly contribute to field failures if they are not properly identified and fixed pre-silicon. Although traditional verification tools such as design rule checking (DRC), layout vs. schematic (LVS) verification and electrical rule checking (ERC) are still required in an integrated circuit (IC) verification flow, they can no longer be the only tools used. This work demonstrates the importance of adding comprehensive reliability checking to the overall IC verification flow to accurately identify reliability issues that cannot be found using traditional verification methods.","PeriodicalId":446436,"journal":{"name":"2022 IEEE International Integrated Reliability Workshop (IIRW)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133839957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-09DOI: 10.1109/IIRW56459.2022.10032756
D. Sangani, J. Diaz-Fortuny, E. Bury, B. Kaczer, G. Gielen
Increasing reliability concerns in advanced technologies have created a significant demand for circuit aging simulation capabilities, so that potential reliability problems can be identified and mitigated pre-production. Recognizing this need, foundries have started to provide aging models with their technology Physical Design Kits (PDK’s). In this work, we present an overview of the aging models and the aging simulation methodology in the PDK of a commercial 28nm bulk technology. The unique features of this work are as follows : (i) comparison of aging model simulations with device-level measurement data obtained at a wide range of {Vgs,Vds} conditions, and (ii) comparison of aging model simulations with circuit-level measurement data. Device- and circuit-level data are then correlated, discrepancies are identified and advantages and pitfalls of these models are highlighted.
{"title":"Assessment of Transistor Aging Models in a 28nm CMOS Technology at a Wide Range of Stress Conditions","authors":"D. Sangani, J. Diaz-Fortuny, E. Bury, B. Kaczer, G. Gielen","doi":"10.1109/IIRW56459.2022.10032756","DOIUrl":"https://doi.org/10.1109/IIRW56459.2022.10032756","url":null,"abstract":"Increasing reliability concerns in advanced technologies have created a significant demand for circuit aging simulation capabilities, so that potential reliability problems can be identified and mitigated pre-production. Recognizing this need, foundries have started to provide aging models with their technology Physical Design Kits (PDK’s). In this work, we present an overview of the aging models and the aging simulation methodology in the PDK of a commercial 28nm bulk technology. The unique features of this work are as follows : (i) comparison of aging model simulations with device-level measurement data obtained at a wide range of {Vgs,Vds} conditions, and (ii) comparison of aging model simulations with circuit-level measurement data. Device- and circuit-level data are then correlated, discrepancies are identified and advantages and pitfalls of these models are highlighted.","PeriodicalId":446436,"journal":{"name":"2022 IEEE International Integrated Reliability Workshop (IIRW)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133361322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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