AN ADDRESS MASKABLE PARALLEL TESTING FOR ULTRA HIGH DENSITY DRAMS

Abstract

This paper describes a new memory array architecture and its related test method named column address-maskable parallel-test (CMT) architecture, suitable for ultra high density DRAMs. We adopt the column address masking technique to achieve effective parallel testing with the least area penalty. The CMT architecture makes it possible to handle various test patterns and to search failed addresses quickly during parallel test operation. In an experimental 64M-bit DRAM, the test time has been reduced to V16K with an area penalty of less than 0.1%.