Statistical analysis and parametric yield estimation of standard 6T SRAM cell for different capacities

Abstract

In advanced CMOS technologies large-scale integration has enabled larger embedded memory capacity in SoCs and it has also necessitated the Static Random Access Memory (SRAM) bitcell qualification requirement of the order of 0.1ppb. This paper presents a qualitative statistical analysis of a 6T standard SRAM cell in read cycle with respect to Static Noise Margin (SNM) due to process parameter fluctuation. The Yield (Y) of SRAM is predicted for different capacities of SRAM array by modeling success/failure boundary through mathematical modeling for one cell. With this frame work, it is demonstrated that the yield can be accurately predicted by increasing the order of the polynomial. The obtained results show that for the first order approximation, the failure probability of a single cell is 2.36×10-6 whereas the failure probability of an SRAM can be decreased to 8.38×10-13 if the success/failure boundary is modeled with a polynomial of order 4.