Bias temperature instability investigation of double-gate FinFETs

Abstract

Double-gate, fin-based Field Effect Transistors (FinFETs) fabricated on silicon-on-insulator (SOI) wafers were subjected to bias temperature instability (BTI) evaluation where focus was placed on the crystallographic sidewall orientation and fin width dependence. For orientation dependence, BTI results at negative stress bias (NBTI) demonstrated that the (110) fin surface degraded more than the (100) surface, because more surface bonds are available in (110) to participate as bond-breaking trap centers during stress. For fin width dependence, positive BTI experienced no dependence on fin width; however, NBTI degradation increased as the fin width narrowed. A plausible cause is a concentration of electrons tunneled from the gate that reside in the SOI fin body. As the fin narrows, the sidewall device channel region moves in closer proximity to these concentrated electrons, which induces more band bending (i.e., increase the surface potential) at the fin/dielectricinterface resulting in a higher electric field and hole concentration in this region during stress, leading to more degradation.