Enabling Automated Sample Delayering, Imaging, and Probing Prep with an Adaptive Endpointing Workflow

Abstract

The development of advanced logic processing technologies has hit a critical slowing period over the past 10 years. Long gone are the booming days of exponential growth seen in chip transistor density as described by Moore's Law back in 1965.[1] With modern logic manufacturers now capable of creating transistors in the 5-7 nm node range, having the ability to isolate, inspect, and probe individual metal and via layers is of utmost importance for defect inspection and design validation. In this realm of failure analysis, it is critical that design manufacturers possess the ability to isolate any given single layer of their logic samples. These isolated layers can be inspected for defects via SEM, provide validation of CAD designs, or tested with electrical probing for failure analysis. The work here-in describes a functional workflow that enables manufacturers to perform this kind of sample preparation in an automated fashion using the Thermo Scientific™ Helios™ G5 PFIB platform. This workflow can be utilized by both the Thermo Scientific Full Wafer and Small Dual Beam PFIB platforms to streamline sample analysis and failure testing in both the lab and fabrication environments.